How to use cpld simulator a mmc
How to use cpld simulator a mmc?
like this mapper:
write data k to 0x5001 then bank prg 0x6000~7fff to page k;
write data k to 0x5002 then set mirror h or v ...
write data k to 0x5010 then rega = k;
write data k to 0x5011 then bank prg 0x8000~9fff to page rega;
how to do in cpld.
How to use cpld simulator a mmc.
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- infiniteneslives
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Re: How to use cpld simulator a mmc.
Draw up the circuit that performs that function for you on paper. Communicate that circuit to the synthesis tool for you CPLD with a hardware description language like verilog or vhdl, something simpler like schematic capture might be a good choice if you're unfamiliar with hardware description languages. Xilinx has schematic capture which done by drawing your schematic in the software which it then converts to a .svf file. Once you have a .svf file you can program your circuit into the CPLD with a JTAG programmer.
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Re: How to use cpld simulator a mmc.
Thanks!infiniteneslives wrote:Draw up the circuit that performs that function for you on paper. Communicate that circuit to the synthesis tool for you CPLD with a hardware description language like verilog or vhdl, something simpler like schematic capture might be a good choice if you're unfamiliar with hardware description languages. Xilinx has schematic capture which done by drawing your schematic in the software which it then converts to a .svf file. Once you have a .svf file you can program your circuit into the CPLD with a JTAG programmer.
I found this:
http://bitcycle.org/electronics/1st_CPLD_project/
http://dangerousprototypes.com/docs/CPL ... ic_devices
- mikejmoffitt
- Posts: 1353
- Joined: Sun May 27, 2012 8:43 pm
Re: How to use cpld simulator a mmc.
I don't know enough about what behavior you want from it exactly, but if you are working in VHDL, you'll want to start with something like this:
That's just a stub and probably could be done a lot better, but it sort of implements the two things you referred to. I didn't even set up outputs yet, but I hope it can point you towards a little bit of the right idea.
Code: Select all
library ieee;
use ieee.std_logic_1164.all;
entity mapper_thing is
port (
addr_in: in std_logic_vector(14 downto 0);
clk_in: in std_logic;
data_in: in std_logic_vector(7 downto 0);
-- For selecting areas in a larger ROM chip than the original bus supports
addr_out: out std_logic_vector(16 downto 0);
data_out: out std_logic_vector(7 downto 0);
mirror_out: out std_logic_vector(1 downto 0);
);
end mapper_thing;
architecture behavior of mapper_thing is
signal current_bank: std_logic_vector(7 downto 0);
signal current_mirror: std_logic_vector(1 downto 0); -- bitfield for HV mirroring?
begin
-- Just a small example to get started; this is by no means functional or complete for any reason
if ( clk'event and clk = '0' ) then -- falling edge of clock
if ( addr_in = "0101000000000001" ) then -- set bank to data value
bank <= data_in;
elsif ( addr_in = "0101000000000010" ) then -- set mirroring
current_mirror <= data_in (1 downto 0);
end if;
-- You should use a signal for this so there are no inferred latches (no good in clock-land)
mirror_out <= current_mirror;
end behavior;