APU length counters, modes and timings

[Bisqwit]

Just curious here: Has there been any new developments and discoveries on how the APU does the length counter timings since 2005, considering that we now also have Visual2a02?

http://wiki.nesdev.com/w/index.php/APU just nonchalantly says that "the exact hardware implementation is not necessarily relevant to an emulator", but it does not even contain information that would be necessary for an emulator to pass all the tests in Blargg's apu_test set.

In particular, where do these timings, from blargg_validated_apu, arise from?

' mode 0
' step 0: 7456 cycles to next step
' step 1: 7458 cycles to next step, also clock length
' step 2: 7457 cycles to next step
' step 3: 1 cycle to next step, also set irq (irq delay 1) (do or don't run linear counter here?)
' step 4: 1 cycle to next step, also set irq (irq delay 1), also clock length
' step 5: 7457 cycles to next step, also set irq (irq delay now+29831) (do or don't run linear counter here?)
' mode 1
' step 0: 7458 cycles to next step, also clock length
' step 1: 7456 cycles to next step
' step 2: 7458 cycles to next step, also clock length
' step 3: 7456 cycles to next step
' step 4: 7454 cycles to next step, don't do anything else

As well as the frame jitter, the exact timings of apu irq, and how exactly the cycle counters are (re)set after a write to $4017 depending on various bits.

(Interestingly enough, blargg's Game_Music_Emu contains a wholly different approach to these step timings.)

[x0000]

I did investigate it all but I didn't correct wiki. Probably will do it when I will have time. If you have specific questions you can ask me in pm.