About DMC and wiki

[Boolean]

http://wiki.nesdev.com/w/index.php/APU#Glossary
The triangle channel's timer is clocked on every CPU cycle, but the pulse, noise, and DMC timers are clocked only on every second CPU cycle

http://wiki.nesdev.com/w/index.php/APU_DMC
bits 3-0 ---- RRRR Rate index
Rate $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D $E $F
------------------------------------------------------------------------------
NTSC 428, 380, 340, 320, 286, 254, 226, 214, 190, 160, 142, 128, 106, 84, 72, 54
PAL 398, 354, 316, 298, 276, 236, 210, 198, 176, 148, 132, 118, 98, 78, 66, 50
The rate determines for how many CPU cycles happen between changes in the output level during automatic delta-encoded sample playback. For example, on NTSC (1.78977267 MHz), a rate of 428 gives a frequency of 1789772.67/428 Hz = 4181.71 Hz.

Since the DMC timer is clocked only on every second CPU cycle, then a rate of 428 should give a frequency of 1789772.67/(2 * 428) Hz = 2090.855 Hz, right?

[lidnariq]

Everywhere on the wiki, that extra factor of two has already been included.

We should be more clear about that.

(In this case, the actual divider is 214. 1789773 Hz ÷(2×214) = 4182Hz)

[Boolean]

Everywhere on the wiki, that extra factor of two has already been included.

We should be more clear about that.

(In this case, the actual divider is 214. 1789773 Hz ÷(2×214) = 4182Hz)

I understand. Thank you.