My emulator always seems to hang on the MMC3 tests.. all of them. I also know why it does this:
When I start the ROM it initializes the APU with all zeroes. Also port 0x4017 a zero is written. This means Inhibit Interrupt Off and the sequencer mode that generates an interrupt in the last step.
Now it comes.. Because of this my emulator Asserts 0x01 on the IRQ line (0x01 = IRQ_PULSE_APU) at the end of a APU frame.
The following code in the IRQ handler will be executed:
--------
ASL $20
STA $E000
RTI
--------
It seems to acknowledge the MMC3 IRQ. But it does not acknowledge the APU interrupt. therefore my emulator immediately returns to the IRQ handler again. Because IRQ_PULSE_APU is still asserted on the IRQ line. Well then this will go on forever.. Never getting any output.
By manually lowering the IRQ_PULSE_APU using a debug command the test will continue and offcourse fail.
What am I missing? because other emulators do run this? Do I not understand something?
Blargg MMC3 tests
Moderator: Moderators
Re: Blargg MMC3 tests
Well, it does disable APU frame irq manually, doesn't it? See test_mmc3.inc:14
Note, that $%11000000 immediately clears frame IRQ flag, that is directly connected to CPU's IRQ line, and makes sure it won't be set until both IRQ inhibit flag and counter mode will change.
Note, that $%11000000 immediately clears frame IRQ flag, that is directly connected to CPU's IRQ line, and makes sure it won't be set until both IRQ inhibit flag and counter mode will change.
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nIghtorius
- Posts: 48
- Joined: Tue Apr 29, 2014 1:31 pm
Re: Blargg MMC3 tests
Well the NES file seem to have different code. As the code @ resetvector is completely different that the included assembly file.
Maybe I should recompile the assembly files and look what will happen.
Maybe I should recompile the assembly files and look what will happen.
Re: Blargg MMC3 tests
The reset routine is at shell.s:44
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nIghtorius
- Posts: 48
- Joined: Tue Apr 29, 2014 1:31 pm
Re: Blargg MMC3 tests
seems that I have a completely different source files:
17-10-2005 01:09 2.286 1.Clocking.asm
17-10-2005 00:41 2.447 2.Details.asm
17-10-2005 01:27 2.235 3.A12_clocking.asm
17-10-2005 00:32 1.569 4.Scanline_timing.asm
17-10-2005 00:54 742 5.MMC3_rev_A.asm
17-10-2005 00:54 839 6.MMC3_rev_B.asm
29-09-2005 23:28 1.724 console.asm
16-10-2005 01:48 2.229 debug.asm
13-10-2005 21:50 2.715 delays.asm
29-09-2005 23:31 3.018 ppu_sync.asm
05-10-2005 14:42 1.716 ppu_util.asm
14-10-2005 01:32 373 prefix_cpu.asm
17-10-2005 00:30 2.744 prefix_mmc3.asm
16-10-2005 23:08 504 prefix_mmc3_validation.asm
15-10-2005 08:38 67 prefix_swap.asm
16-10-2005 01:17 403 runtime_swapcart.asm
09-10-2005 19:39 2.322 validation.asm
Unable to find test_mmc3.inc or shell.s
17-10-2005 01:09 2.286 1.Clocking.asm
17-10-2005 00:41 2.447 2.Details.asm
17-10-2005 01:27 2.235 3.A12_clocking.asm
17-10-2005 00:32 1.569 4.Scanline_timing.asm
17-10-2005 00:54 742 5.MMC3_rev_A.asm
17-10-2005 00:54 839 6.MMC3_rev_B.asm
29-09-2005 23:28 1.724 console.asm
16-10-2005 01:48 2.229 debug.asm
13-10-2005 21:50 2.715 delays.asm
29-09-2005 23:31 3.018 ppu_sync.asm
05-10-2005 14:42 1.716 ppu_util.asm
14-10-2005 01:32 373 prefix_cpu.asm
17-10-2005 00:30 2.744 prefix_mmc3.asm
16-10-2005 23:08 504 prefix_mmc3_validation.asm
15-10-2005 08:38 67 prefix_swap.asm
16-10-2005 01:17 403 runtime_swapcart.asm
09-10-2005 19:39 2.322 validation.asm
Unable to find test_mmc3.inc or shell.s
Re: Blargg MMC3 tests
Are you sure you're running the latest version of the test?
Quietust, QMT Productions
P.S. If you don't get this note, let me know and I'll write you another.
P.S. If you don't get this note, let me know and I'll write you another.
Re: Blargg MMC3 tests
For this old version the test begins before shell init, so it is actually the routine named reset in each asm file. Again, frame IRQ is disabled at the start, see prefix_mmc3.asm:11 (I believe it has a fixed address in the ROMs, $e0b5 / $a0b5)
UPD.
UPD.
I don't see it anywhere in old version, it is in a new one (at address $e2bc, test_mmc3.inc:126). Fishy...nIghtorius wrote: ASL $20
STA $E000
RTI