HuC6280 opcode TST #ARG, EA is the following:
sta temp
lda EA
and #ARG
php
lda temp
plp
EA (effective address) is ZP, ZP+X, ABS, and ABS+X.
It sets the zero flag accordingly, but TST also sets bit #7 (N flag) and bit #6 (V flag) of the processor flag as well. Which, IIRC and according to my cribsheet, means bits 7 and 6 of the ARG is what will be in those corresponding flag bits (N and V). You can't use PHA/PLA because PLA sets bit #7 of the processor flag on most (all?) 65x processors.
Edit: Hmm, looks like even that code would work. AND doesn't set bit #6 (V) in the flag register.
Edit2:
If you know for a fact that the code you're replacing, with a macro, is not testing or branching on the N and V flags from the TST opcode, then you can get away with this:
sta temp
lda EA
and #ARG
php
lda temp
plp
But if it does use N/V, then you'll have to write a macro to extract that state and still keep Z bit state. Or replace the logic with some other code.
Edit 3: Hmm...
Probably use BIT opcode. I think would behave exactly the same as TST. According my cribsheet (though for 6280), Z results from BIT operation, and N/V are loaded from the operand of BIT. I assume this is the same behavior on other 65x processors. So...
