nesdev.org

Posted: **Mon Dec 15, 2014 3:52 pm**

Hi,

I recently registered in the forums but I've been reading them and the Wiki for several months now, and I have to say that the info you guys have compiled along these years is gold.

So, I decided to start my own NES emulator (just for fun). Right now, I've finished my CPU core and it passes Nestest.nes, and Blargg's Official / Unofficial instructions tests.

I have also come up with a PPU that shows most of the NROM games. The problem is that I can't seem to pass all of Blargg's ppu_vbl_nmi tests.

Currently I get the following results:

01-Vbl_Basics - PASS
02-Vbl_set_time - PASS
03-Vbl_clear_time - PASS
04-NMI_control - PASS
05-nmi_timing - FAIL
06-supression - FAIL
07-nmi_on_timing - FAIL
08-nmi_off_timing - FAIL
09-even_odd_frames - PASS
10-even_odd_timing - PASS

So, I'm a bit stuck here. I seem to have my frame timing correct (The VBL flag sets and clears correctly, odd / even frames are OK).

CPU polls for interrupts at the second to last cycle of every instruction, except for branches, that behave differently (polled before the 2nd cycle and polled again if there's a page cross).

Can you guys, give me some hints so I can start looking at the right place for passing test 05 (and then i can start working my way for passing the remaining ones?

: 5-NMI_Timing_Fail.png (18.62 KiB) Viewed 2232 times

Sorry for my poor English.

Thanks!

Posted: **Wed Dec 17, 2014 2:24 am**

Do you know what those numbers mean?

This is the pattern that should be
; 00 4
; 01 4
; 02 4
; 03 3
; 04 3
; 05 3
; 06 3
; 07 3
; 08 3
; 09 2

look in the code of rom

Code: Select all

; Tests NMI timing.
;
; Prints which instruction NMI occurred
; after. Test is run one PPU clock later
; each line.
;
; 00 4
; 01 4
; 02 4
; 03 3
; 04 3
; 05 3
; 06 3
; 07 3
; 08 3
; 09 2

CUSTOM_NMI=1
.include "shell.inc"
.include "sync_vbl.s"

zp_byte nmi_data

nmi:    stx nmi_data
	rti

main:   jsr console_hide
	loop_n_times test,10
	check_crc $A6CCB10A
	jmp tests_passed

test:   jsr print_a
	jsr disable_rendering
	jsr sync_vbl_delay
	delay 29749+29781
	lda #$FF
	sta nmi_data
	ldx #0
	lda #$80
	sta $2000
landing:
	; NMI occurs after one of these
	; instructions and prints X
	ldx #1
	ldx #2
	ldx #3
	ldx #4
	ldx #5
	
	lda #0
	sta $2000
	lda nmi_data
	jsr print_dec
	jsr print_newline
	rts

See the routine "main"; there is the line "loop_n_times test, 10" which
means "test" will run 10 times.

In routine "test" there is a code of sync with the NMI.

Look into "landing", "NMI" supposedly should run three times
after "LDX #4", six times after "LDX #3" and one after the "LDX #2".

register "X" is stored in "nmi_data" and displayed each pass.

In your test had only 5's, all this means that your "NMI" takes too long to be triggered.

Posted: **Tue Dec 30, 2014 11:09 am**

I figured out the problem. It was certainly a straight forward thing to fix.... XD.

My CPU was polling for interrupts incorrectly, so the NMI was being fired at the wrong time. I made sure interrupts were polled just before the last cycle of every instruction. Also checked that the dummy reads / writes, page crossings and branch timings were correctly implemented. That solved it.

¡Gracias Nostromo!

nesdev.org

Help with passing Blargg's ppu_vbl_timing tests.

Help with passing Blargg's ppu_vbl_timing tests.

Re: Help with passing Blargg's ppu_vbl_timing tests.

Re: Help with passing Blargg's ppu_vbl_timing tests.