Due to the delay behind m2 on romsel, there is a bus conflict at the first 33ns of M2 positive pulse in accessing $8000 - $ffff and $0 - $7fff. The write operation at the address of $e000 - $ffff will gate the wram of $6000 - $7fff a short while, and then access the real address of $e000 - $ffff.krzysiobal wrote: ↑Thu Jun 10, 2021 5:03 amWhy you and author of the wiki's article consider it as something special? What would you expect on the PRG lines without that "special feature" when accesing $6000 when RAM is enabled? Zeroes? Ones? Tri-state? Then it would be surprisingly special.
The mux inside FME that chooses between one of four PRG registers takes into account just CPU-A14, CPU-A13 and ROMSEL and nothing more. It does not care about the RAM/ROM bit because that would be waste of resources.
Then maybe we should also add a note that the E bit is just a general purpose output latch, that can be alternatively used as PRG-RAM-A13, PRG-ROM-A19 or something other that you wouldn't even dream of. Just no games take care of that.
MMC3, for example, outputs ones on PRG lines when accessing $6000-$7fff not because it does not have PRG banking feature, but because ROM is only enabled at $8000-$ffff, and so the mux only takes into account CPU-A14, CPU-A13 and the PRG mode bit), so it has no physical ability to distinguish $6000 from $e000..
The write register of fme-7 is not in the range of $e000 - $ffff. Therefore, even if the CS of wram has no hardware delay, it will not be written unexpectedly.
In addition, The active high CS1 of SRAM is controlled by E-bit. Because it can control two CS logics, the protection of SRAM will be better.