FCEUX and Nintendulator both support iNES 2, and don't have a fallback that uses byte 8 for RAM size.
I can't find a single ROM in my collection that doesn't have 0 in that byte, though.
Moderator: Moderators
Even then, it's 2x 6116 chips.lidnariq wrote:The only 4KiB SRAM I've ever seen is the nametable memory used in the Vs. System.
tepples wrote:This would provide ample space for a Z-machine or BASIC interpreter.
tpw_rules in #nesdev is working on one.Drag wrote:...and then comes the game that uses it.
Uh...? The schematic claims it's a TC5533P-A 4 KiB SRAM. And a random picture shows a TC5533P-B 4 KiB SRAM.l_oliveira wrote:Even then, it's 2x 6116 chips.lidnariq wrote:The only 4KiB SRAM I've ever seen is the nametable memory used in the Vs. System.
I stand corrected. Thank you !lidnariq wrote:Uh...? The schematic claims it's a TC5533P-A 4 KiB SRAM. And a random picture shows a TC5533P-B 4 KiB SRAM.l_oliveira wrote:Even then, it's 2x 6116 chips.lidnariq wrote:The only 4KiB SRAM I've ever seen is the nametable memory used in the Vs. System.
To be honest, if I hadn't seen it there, I would have assumed 4 KiB SRAMs didn't exist.
Code: Select all
PRG Bank 0 ($8)
7 bit 0
---- ----
ERbB BBBB
|||| ||||
||++-++++- The bank number to select at CPU $6000 - $7FFF
|+------- RAM / ROM Select Bit
| 0 = PRG ROM
| 1 = PRG RAM
+-------- RAM Enable Bit (6264 +CE line)
0 = PRG RAM Disabled
1 = PRG RAM Enabled
Code: Select all
ER $6000-$7FFF
00 PRG ROM
01 Open Bus
10 Open Bus*
11 PRG RAM
*Not a recommended setting value.
**Although FME-7 has the bank switching capability of PRG RAM, no game relies on it.
***FME-7 has better bus anti-interference performance than MMC3 in the address range of $6000-$7FFF.
Why you and author of the wiki's article consider it as something special? What would you expect on the PRG lines without that "special feature" when accesing $6000 when RAM is enabled? Zeroes? Ones? Tri-state? Then it would be surprisingly special.