iNES Mapper 12 (MMC3A?)

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lidnariq
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Re: iNES Mapper 12 (MMC3A?)

Post by lidnariq »

You should only have to rewire one wire on the PCB, no need for ROM patching.
Ruslansh
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Re: iNES Mapper 12 (MMC3A?)

Post by Ruslansh »

I did so. Address A5 switched to A11. All sprites were fixed, but several remained buggy. Then I returned the addresses all back and corrected the address 4800 to 4132, all the sprites were corrected, but the Indian and a few more rights were distorted. That is, soldering the address or changing the game gives the same result.
lidnariq
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Re: iNES Mapper 12 (MMC3A?)

Post by lidnariq »

For whatever it's worth, Kung Lao has glitchy tiles even in an emulator.
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krzysiobal
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Re: iNES Mapper 12 (MMC3A?)

Post by krzysiobal »

Just saw wiki article about this mapper.
Huang-1 has identical pinout to the C5052-13.

GAL16V8 is connected as follows:

Code: Select all

 +-------------------------------------------+
 |              +---v---+                    |
 +->- CLK_IN -> |01   20| -- VCC             |
      CPU_D1 -> |02   19| -> CLK_OUT ->------+
 CPU_nROMSEL -> |03   18| -> CHR_A18
     CPU_A14 -> |04   17| -> MPR_PPU_A12
     CPU_A13 -> |05   16| -> MPR_MODE
      CPU_A8 -> |06   15| -> O2 (feedb)
     CPU_RnW -> |07   14| -> O3 (feedb)
     PPU_A12 -> |08   13| <- CPU_D4
          M2 -> |09   12| <- CPU_D0
         GND -- |10   11| <- GND (/nOE)
                +-------+
                 GAL16V8
Quessed equations:             
  CLK_OUT <=
      '0' when CPU_M2 = '1' AND CPU_NROMSEL = '1' AND CPU_A14 = '1' AND CPU_A13 = '1' AND CPU_A8 = '1' AND CPU_RNW = '0' ELSE
      '1';
  
  O2.D := CPU_D0
  O2.CLK := CLK_IN
  
  O3.D := CPU_D4
  O3.CLK := CLK_IN
  
  MPR_MODE.D := CPU_D1
  MPR_MODE.CLK := CLK_IN
  
  CHR_A18 <=
      O2.D WHEN PPU_A12 = '0' ELSE
      O3.DS

There can't be any solder jumper underneath PAL for language select, because all PAL pins are already used (I am a little unsure about pin, but it is probably GND)

This GAL also controls Huang's MODE pin (VCC=MMC3, GND=VRC2, NC=MMC1) and it has CPU D1 routed in, which wiki does not mention.
Because this game always writes to $4132 value with bit D1 set, I assume that state of this bit is directly latched to the MPR_MODE pin.

Good question is in what mode the gal is configured.
* If GAL is in complex mode, pin 11 could be used as input, but that would limit pins 19 and 12 to be outputs only, which would conflict with the current use of pin 12 as input CPU_D0.
*If GAL is in `simple mode`, all its outputs would be always enabled, MPR_MODE could output only 0/1 and pin 11 could be potentially input (O2 and O3 outputs would be feedback-latches instead of Q-flip flops)
*If GAL is in `registered mode`, pin 11 has to be GND, but it still allows MPR_MODE to be feedback-loop latch with configurateble /OE

Code: Select all

D~7654 3210 (write)
  ---------
  ...B ..MA
     |   |+- CHR A18 when PPU A12=0
     |   +-- MODE: MMC3=1, ???=0   (can be low or highimpedance)
     +------ CHR A18 when PPU A12=1
* Whichi is also unclear for me, why this PAL constrols HUANG's PPU-A12.
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