I had some branch timing test ROMs mostly written and the recent thread prompted me to finish them. They test branch timing and the edge cases for page crossings that an emulator might get wrong. I also wrote a concise summary of timing (below).
An untaken branch takes 2 clocks. A taken branch takes 3 clocks. A taken branch that crosses a page takes 4 clocks. Page crossing occurs when the high byte of the branch target address is different than the high byte of the address of the next instruction:
i took a break from my ppu to work on timing and do not have nmi timing down yet. ill have to work on that. do these test depend on the odd from ppu tick being dropped ? i assume that they do. or if all the test are run with the ppu off first then turn it on. but then i suppose the nmi isnt set with the ppu off ?
I don't think I depend on any exotic PPU behavior, just the NMI occuring every ~29780 CPU clocks. There would be no reason to rely on anything more than that. At reset it just enables NMI and then runs sequences and uses the NMI to time them. I made them fairly loose so your NMI can probably be inaccurate by a few clocks.
i was thinking about the nmi... i just ran my cpu for 29780 cycles since the nmi is predictable.
an interesting test would be to catch the invalid and dummy reads. i recall you tested this before and determined that repeated reads do effect the ppu. perhaps test the repeated reads, invalid reads.
ill have to think of a way to test that. not sure you would be interested.
