higan CPU emulation mode bug? (attn: byuu or any 65816 guru)

[Near]

... there is no "the bus", there's a whole bunch of separate buses all over the place.

I get that there are ones of different importance levels, and this one's probably the most important, but yeah.

[qwertymodo]

Well, right. I know that. Same idea, but one for each bus.

[AWJ]

I like the bitmask idea for level-sensitive interrupt lines. For the SNES CPU IRQ you'd have one bit for the h/v counter, one bit for the cartridge slot and one bit for the expansion port.

Does higan emulate anything with an edge-sensitive interrupt line fed from multiple sources?