PPU help

[Muhammad_R4]

Hello Nes developers , I need your help

I am studying electronics and digital systems design engineering , I heared about NES PPU and I want to implement it using ahardware description language

I have read many but till now there is nothing explaining the internal components of the ppu , all talking about pattern tables , name table , ...etc but I need to know more about the hardware and how it renders the graphics from the tables till reaching the TV with them , I am willing to make it compatible with the micro-processor we designed in the university.

I want to know more about the hardware of PPU to implement it using a HDL , I need not to know an overview.

thanks in advance.

[Dwedit]

I think you want this page: http://wiki.nesdev.com/w/index.php/PPU_rendering

Quick summary of rendering backgrounds:
Read byte from nametable
Read byte from attribute table
Read pattern table byte #1
Read pattern table byte #2
Then you have 8 pixels of background ready.

In order to have pixels ready by the time it starts drawing the image, it actually fetches the first 16 pixels of background before it starts drawing it out.
Fine X scroll is used to determine where in the buffer it draws background pixels from.

It uses the "V" address as counters for this process, then increments the vertical parts of "V", and sets the horizontal parts back to "T" address when it reaches the end of a scanline.

To actually make the colors, it uses square waves at different phases and different voltage levels, see http://wiki.nesdev.com/w/index.php/NTSC_video

[Muhammad_R4]

right , I want something like this but in much details , I want anything that explain PPU as harwdare from A to Z

[Dwedit]

I don't know the best way to actually implement hardware in an HDL, but if you can get the repeated 4 reads working, and have it spit out pixels, that's a good start.

[Muhammad_R4]

Can you explain what do you mean by " the repeated 4 reads working, and have it spit out pixels," ? I didn't get it sorry .

[thefox]

This doc is closest to "hardware level" description that I know of: http://nesdev.com/2C02%20technical%20reference.TXT. It's over 10 years old, so it may contain some mistakes.

Most other docs are written from a behavioral point of view. They have all the information you would need for a hardware implementation, but it's your job to make sense of them and translate accordingly.

[tepples]

Over the course of a scanline, the PPU reads bytes from video memory and uses the data to generate a background picture. This means "the repeated 4 reads working" refers to the "Quick summary of rendering backgrounds" that Dwedit mentioned.

Read byte from nametable
Read byte from attribute table
Read pattern table byte #1
Read pattern table byte #2

The wiki page "PPU rendering" describes in which order the PPU reads bytes of data from video memory, and for what purpose each byte of data read from video memory is used. If you reproduce these, you can make a PPU subset that renders a background.

"and have it spit out pixels" refers to a set of latches and shift registers that the PPU uses to decode the planar pixels (which means pixels separated into bit planes) into.

Have you ever developed a program for the NES? Or are you only trying to emulate existing ROMs?

I noticed from the way you left spaces around commas and quotation marks that English may not be your first language.

[Muhammad_R4]

Over the course of a scanline, the PPU reads bytes from video memory and uses the data to generate a background picture. This means "the repeated 4 reads working" refers to the "Quick summary of rendering backgrounds" that Dwedit mentioned.

Read byte from nametable
Read byte from attribute table
Read pattern table byte #1
Read pattern table byte #2

The wiki page "PPU rendering" describes in which order the PPU reads bytes of data from video memory, and for what purpose each byte of data read from video memory is used. If you reproduce these, you can make a PPU subset that renders a background.

"and have it spit out pixels" refers to a set of latches and shift registers that the PPU uses to decode the planar pixels (which means pixels separated into bit planes) into.

Have you ever developed a program for the NES? Or are you only trying to emulate existing ROMs?

I noticed from the way you left spaces around commas and quotation marks that English may not be your first language.

You are right , English is not my 1st language
I am not trying to develop NES program or emulate a ROM , I am trying to implement NES graphic card from hardware point of view to apply what I have learned about micro-processor design in a simple graphic card such as PPU.

[Muhammad_R4]

This doc is closest to "hardware level" description that I know of: http://nesdev.com/2C02%20technical%20reference.TXT. It's over 10 years old, so it may contain some mistakes.

Most other docs are written from a behavioral point of view. They have all the information you would need for a hardware implementation, but it's your job to make sense of them and translate accordingly.

Can you put links to the other docs you are talking about ? may them help me.

I have no problem no with the behavioral point of view , my problem is that there are many things are uncovered and others seem ambiguous to me

[thefox]

I was mainly referring to the NESDev Wiki (which was linked earlier).

[Jeroen]

This doc is closest to "hardware level" description that I know of: http://nesdev.com/2C02%20technical%20reference.TXT. It's over 10 years old, so it may contain some mistakes.

Most other docs are written from a behavioral point of view. They have all the information you would need for a hardware implementation, but it's your job to make sense of them and translate accordingly.

Can you put links to the other docs you are talking about ? may them help me.

I have no problem no with the behavioral point of view , my problem is that there are many things are uncovered and others seem ambiguous to me

Not to sound too antagonizing, but other's have made FPGA implementations with LESS info available than on the wiki. Imo it's about as detailed as you can get.

Can you perhaps give an example of a document that would be close to the level of information you expect? (say a different CPU)

[Dwedit]

So, um, what specific questions do you have?

[Muhammad_R4]

I think of it as follows :

when we designed our micro-processor , we had a RTL schematic showing all registers , memories , hardware signals and everything hardware related to the processor

I tried to do the same but I failed , that's why I am asking for a document explaining all this

[Jeroen]

That's because that plain does not exist for the NES ppu. All implementations other people have done were made by implementing the logic themselves based on what they knew the registers etc should do.

edit: To clarify, that means the "RTL schematic". Obviously the wiki has info on registers etc. Even some on timing (but not bus timing)

[Quietust]

We don't have an RTL schematic of the PPU - the best we have is a transistor-level schematic (in the form of the Visual 2C02), and it isn't so much a schematic as it is a netlist.