PPU pinout

[Muhammad_R4]

Hello NES dev

I have a question related to PPU pins.
http://wiki.nesdev.com/w/index.php/PPU_ ... escription

I am confused with the address and data buses, mainly, what can I address other than the 8 PPU registers? and what else can I read on the data bus ?

I think they cannot access the internal memories as they have their own internal access registers, if so, why there are 13 bit in the address bus ? aren't 3 only enough and the CS for mapping ?

thank's in advance.

[mikejmoffitt]

The PPU uses those address pins to address graphics memory (CHR ROM, CHR RAM). While the CPU really only needs to control A0-A2 to write to the PPU, the PPU will drive AD0-AD7 and A8 and upwards (A8 is not the 2A03's A8).

[Bregalad]

It's the adress bus of the PPU itself, adressingin the VRAM adress space.

On the CPU adress bus, the PPU is slave and responds to adress $2000-$2007 (and, if I'm not mistaken, mirrored up to $3fff). On the PPU address bus, the PPU is master and exept VRAM to respond at $0000-$1fff for pattern tables and at $2000-$3fff for name and attribute tables.

The palette is on yet anohter bus and is completely internal to the PPU, as is the OAM.

[Muhammad_R4]

So, as I now understood ( and tell me if I get it right or not )

in the VBlank period , the CPU uses A2 A1 A0 to write to the registers, otherwise , during the rendering , A13-->A0 are used by the internal registers to access the VRAM

while the PAL memory and the OAM are on separate buses and have no relation with those.

[mikejmoffitt]

So, as I now understood ( and tell me if I get it right or not )

in the VBlank period , the CPU uses A2 A1 A0 to write to the registers, otherwise , during the rendering , A13-->A0 are used by the internal registers to access the VRAM

I do not think that is quite correct - A2 A1 A0 are the 2A03's address pins, which are used for selecting PPU registers to write to. During rendering these pins aren't driven by the PPU externally, otherwise it would interfere with CPU operation. I think

the PAL memory and the OAM are on separate buses and have no relation with those.

Yes, they are only accessed indirectly by the CPU or internally by the PPU.

[rainwarrior]

I think the description on the Wiki should really change its terminology. It's not appropriate for one pin to be labelled A0 for the CPU bus, and then also label something A9 for the PPU bus.

I'll just make a quick change...

[Bregalad]

In my opinion, the label of those buses should be identical to those of the cartridge connector. That is, CPU Ax and CPU Dx are used for the CPU bus, and PPU Ax and PPU Dx are used for the PPU data bus. When not specified, the CPU bus is referred to by default. The PPU bus should never be menionned without prefixing signal names with "PPU", ever.

So, as I now understood ( and tell me if I get it right or not )

in the VBlank period , the CPU uses A2 A1 A0 to write to the registers, otherwise , during the rendering , A13-->A0 are used by the internal registers to access the VRAM

while the PAL memory and the OAM are on separate buses and have no relation with those.

No, you don't appear to understand.

CPU A0-A2 registers is used to adress the PPU memory mapped IO registers at $2000-$2007, and at any time, VBlank or not.

The PPU has it's hard logic to fetch pattern, name and attribute table from VRAM outside of VBlank. During VBlank or forced blanking, the PPU Ax pins will pretty much mirror the address written to $2006 (I have no idea if they stay there when read/write signal is not active, but I don't see what other value the adress lines could take). A read or write to $2007 on the CPU side will be immediately followed by a similar read or write to the PPU bus. This also explains the buffered $2007 reads.

Writing to palette area will do something internally directly and will not mirror on the PPU bus, exept maybe the adresses will show up (this would have to be verified).

[rainwarrior]

In my opinion, the label of those buses should be identical to those of the cartridge connector. That is, CPU Ax and CPU Dx are used for the CPU bus, and PPU Ax and PPU Dx are used for the PPU data bus. When not specified, the CPU bus is referred to by default. The PPU bus should never be menionned without prefixing signal names with "PPU", ever.

Ah, yeah, that's a better idea. Thanks. There's an old diagram that called them RS0-2 but I think "CPU A0" and "PPU A10" makes things crystal clear.

[Muhammad_R4]

No, you don't appear to understand.

CPU A0-A2 registers is used to adress the PPU memory mapped IO registers at $2000-$2007, and at any time, VBlank or not.

then the registers can be edited during rendering ? if so does the effect also appear outside the VBlank or their effect works when the frame ends ?

[tepples]

During forced blank (write $00 to $2001), video memory can be updated the same way as during vertical blank: through $2006 and $2007. Palette changes will produce visible artifacts though.

During rendering, scroll splits use $2005 and $2006.

[rainwarrior]

Several of the registers are commonly used outside of vblank:

$2000 - less commonly used mid-screen, but can switch tile sets, etc.

$2001 - can be used to turn sprites on or off mid-screen to keep them from overlapping a status bar, toggle colour emphasis for a water effect or as a timing diagnostic.

$2002 - commonly polled for sprite 0 hit to time other effects (e.g. SMB status bar)

$2005 - commonly used for horizontal scrolling changes mid-screen (e.g. SMB status bar, again)

$2006 - required for vertical scrolling changes mid-screen


The other registers $2003/2004/2007 are not normally used outside of vblank.

[Muhammad_R4]

I somehow got it, but still I have a question

as far as I know, the game should prepare the graphics for the next frame during the Vblank , and also the VRAM address, VRAM data -as I think - are able to modify the data for the next frame

that's why I thought that they are used in the Vblank only to update the graphics.

now you all said that they can be used any time, so:
1. why would I need to access them inside rendering ( I mean Vram addr, Vram data , OAM addr, OAM data)
2. Am I true that the PPU use those mentioned registers to update graphics ( nametables , patterns , attributes and OAM ) ??

[tepples]

When rendering is off and the screen is therefore blank, video memory can be modified at any time. When rendering is on, video memory can be modified only during vertical blank.

You change the video memory address during rendering to have the top and bottom of the screen use different scroll positions, such as for a status bar or parallax scrolling.

[Bregalad]

then the registers can be edited during rendering ? if so does the effect also appear outside the VBlank or their effect works when the frame ends ?

The CPU can adress memory mapped I/Os at $2000-$2007 anytime. Rainwarrior summarized what usage of them can be done outside of Vblank, but the CPU can read and write them anytime, it will create an undefined behaviour when accessing VRAM (or OAM) during rendering.

now you all said that they can be used any time, so:
1. why would I need to access them inside rendering ( I mean Vram addr, Vram data , OAM addr, OAM data)

You should not access VRAM data ($2007) nor OAM adress or OAM data during rendering. This is undefined behaviour.

VRAM ADR ($2006) is shared with scrolling registers, so changing it affects scrolling and can create interesting raster effects.

2. Am I true that the PPU use those mentioned registers to update graphics ( nametables , patterns , attributes and OAM ) ??

Yes, VRAM is accessed exculively with $2006 and $2007, with the exeption of OAM, which is mostly accessed through sprite DMA. via $4014. When the programm write to $4014, the NES CPU will automatically jaét tje 6502 and perform a chain of reads from memory followed by a write to $2004, and this 256 times. On the PPU side, it's as if $2004 was written to 256 times very quickly.

$2004 is very rarely used on it's own.

[Muhammad_R4]

VRAM is accessed exculively with $2006 and $2007

I have a question here, I searched in the PPU registers documentaion about how the PPU differentiate between the read to VRAM and the write to it through both registers , but I found nothing