Page 21 of 21

Re: Introducing the VeriSNES (FPGA-based SNES)

Posted: Fri Oct 12, 2018 5:20 pm
by Torlus
Hi,

I just came across this topic, this VeriSNES project looks awesome!
I've written some FPGA cores too, especially SEGA Genesis/Megadrive, PC-Engine/TurboGrafx-16 (both in VHDL) and Atari Jaguar (Verilog).
See my site http://lvt.tl/ for more information, and my GitHub repos https://github.com/Torlus

Is there any way I could help, if needed ?
What about the current status of the project, especially licensing/source status (open or closed) ?

Regards,
Gregory

Re: Introducing the VeriSNES (FPGA-based SNES)

Posted: Sat Oct 13, 2018 4:47 am
by retrorgb
Those are some impressive cores! Would you consider porting them to the MiSTer project?: https://github.com/MiSTer-devel/Main_MiSTer/wiki

Re: Introducing the VeriSNES (FPGA-based SNES)

Posted: Sat Oct 13, 2018 6:15 am
by Torlus
retrorgb wrote:Those are some impressive cores! Would you consider porting them to the MiSTer project?: https://github.com/MiSTer-devel/Main_MiSTer/wiki
Already done. ;) Except for the Atari Jaguar where the requirements are too high.

Re: Introducing the VeriSNES (FPGA-based SNES)

Posted: Sat Oct 13, 2018 6:50 am
by retrorgb
Wow, thank you! Too bad about the Jag! I wonder if it's powerful enough to run a SNES core as well?

Re: Introducing the VeriSNES (FPGA-based SNES)

Posted: Sat Oct 13, 2018 11:26 am
by Torlus
retrorgb wrote:Wow, thank you! Too bad about the Jag! I wonder if it's powerful enough to run a SNES core as well?
As the Genesis/Megadrive core works, I’d say yes.
However, this will remain a supposition until I can see the source code.

Re: Introducing the VeriSNES (FPGA-based SNES)

Posted: Sat Oct 13, 2018 1:11 pm
by syboxez
retrorgb wrote:Wow, thank you! Too bad about the Jag! I wonder if it's powerful enough to run a SNES core as well?
Yes it is. The Super NT's FPGA is approximately half the size of the one in the MiSTer, and VeriSNES has already been ported to the MiSTer: https://www.youtube.com/watch?v=7ae5iUe8diY

Re: Introducing the VeriSNES (FPGA-based SNES)

Posted: Mon Oct 29, 2018 11:04 am
by cacophony
jwdonal, can you reconsider releasing the source for the benefit of MiSTer and other future community driven FPGA solutions? From a preservation perspective it would be of large benefit, and you might even make some money from your goodwill if you also have a patreon account.

And with the open source SD2SNES now supporting pretty much all the desired special chip games, there could presumably be a single device FPGA solution to playing essentially all of the SNES library (as I'm sure somebody would port that code to the MiSTer).

Re: Introducing the VeriSNES (FPGA-based SNES)

Posted: Thu Nov 15, 2018 3:48 pm
by Reed Solomon
Torlus wrote:
retrorgb wrote:Those are some impressive cores! Would you consider porting them to the MiSTer project?: https://github.com/MiSTer-devel/Main_MiSTer/wiki
Already done. ;) Except for the Atari Jaguar where the requirements are too high.
That may not be the case. There are people like ElectronAsh working on porting your Jaguar core to mister. Maybe check it out and see how it's going?