DMA and dram refresh cycle

[srg320]

I create a SNES on FPGA. And now I tested several small games with simple LoROM mapper (Dr.Mario, Super Mario World 1, Tetris Attack, Battletoads, Tom and Jerry, Daffy Duck, Sim Sity). All tested games works well. But one game (Sim Sity) works with damaged sprites (and backgrounds, and objects).

I found that the problem disappears if I temporarily remove dram refresh mode in SCPU module. I'm thinking the problem in DMA. I can't understand how DMA should work during dram refresh cycle.

[creaothceann]

(Afaik) DMA can't work during DRAM refresh; for each cycle of the 21MHz clock the 5A22 has these priorities:

Code: Select all

1. [if DRAM refresh] step the DRAM refresh state machine
2. [if DMA]          if DMA      delay counter = 0 then step the DMA engine;  increment the DMA      delay counter (reset at 8)
3.                   if bus hold delay counter = 0 then step the 65c816 core; increment the bus hold delay counter (reset at 6, 8 or 12, depending on the value on the 65c816 core's address bus)

[srg320]

You're right, and I did the same in my project, active REFRESH signal disable CPU core and DMA, only delay counter I have one (common for DMA and 65c816). I'll rewrite the code DMA/HDMA.

2. [if DMA]          if DMA      delay counter = 0 then step the DMA engine;  increment the DMA      delay counter (reset at 12)

In my opinion: for DMA reset at 8.

[creaothceann]

Yeah... fixed.