Mesen-S - SNES Emulator

[93143]

I found that d4s' Breath of Fire II (German) fan translation's streaming HDMA audio engine was extremely timing sensitive, and didn't work well at 32000hz.

If it's similar to the one in N-Warp Daisakusen, he just dumps the contents of the four ports to the stack as quickly as possible and then twiddles his thumbs to make up 66 cycles. Which is a bit long even for PAL. I can see why a low value for the SMP speed could cause issues, depending on how soon after the first write he starts reading, and on how long the bursts are.

[Near]

How hard would it be to build an 8:7 PLL to turn the 21.47 MHz master clock into 24.55 MHz to give 31960.2 Hz output?

The hard part for me would be performing the soldering work.

[klurey]

It's possible Kishin Douji Zenki - Tenchi Meidou is getting stuck because it keeps writing CPU 2141 and resetting SPC F1 at around same time? Forever loop on both sides.


https://wiki.superfamicom.org/spc700-reference

There will probably be some conflict if the snes writes data at the same time the SPC initiates a port clear function.

Some emulators don't emulate this, BSNES does though.

[klurey]

behavior on simultaneous read+write from the SPC+CPU

When cpu reads / spc writes to same port simultaneously, bsnes keeps returning old value.

Code: Select all

da03dc bra $03d9     [da03d9] A:32 H:1200
da03d9 lda $2140     [002140] A:32 H:1218
da03dc bra $03d9     [da03d9] A:32 H:1242
da03d9 lda $2140     [002140] A:32 H:1260

..096c mov   $0f4,a           A:33

da03dc bra $03d9     [da03d9] A:32 H:1284
da03d9 lda $2140     [002140] A:32 H:1302
da03dc bra $03d9     [da03d9] A:32 H:1326
da03d9 lda $2140     [002140] A:32 H:1344

..096e inc   a                A:33

da03dc bra $03d9     [da03d9] A:33 H:   4
da03d9 lda $2140     [002140] A:33 H:  22

..096f bra   $096c            A:34

da03dc bra $03d9     [da03d9] A:33 H:  46
da03d9 lda $2140     [002140] A:33 H:  64
da03dc bra $03d9     [da03d9] A:33 H:  88
da03d9 lda $2140     [002140] A:33 H: 106

..096c mov   $0f4,a           A:34

da03dc bra $03d9     [da03d9] A:33 H: 130
da03d9 lda $2140     [002140] A:33 H: 148
da03dc bra $03d9     [da03d9] A:33 H: 172
da03d9 lda $2140     [002140] A:33 H: 190

..096e inc   a                A:34

da03dc bra $03d9     [da03d9] A:34 H: 214
da03d9 lda $2140     [002140] A:34 H: 232

..096f bra   $096c            A:35

da03dc bra $03d9     [da03d9] A:34 H: 256
da03d9 lda $2140     [002140] A:34 H: 274
da03dc bra $03d9     [da03d9] A:34 H: 298
da03d9 lda $2140     [002140] A:34 H: 316

..096c mov   $0f4,a           A:35

da03dc bra $03d9     [da03d9] A:34 H: 340
da03d9 lda $2140     [002140] A:34 H: 358
da03dc bra $03d9     [da03d9] A:34 H: 382
da03d9 lda $2140     [002140] A:34 H: 400

..096e inc   a                A:35

da03dc bra $03d9     [da03d9] A:35 H: 424
da03d9 lda $2140     [002140] A:35 H: 442

..096f bra   $096c            A:36

da03dc bra $03d9     [da03d9] A:35 H: 466
da03d9 lda $2140     [002140] A:35 H: 484
da03dc bra $03d9     [da03d9] A:35 H: 508
da03d9 lda $2140     [002140] A:35 H: 526

..096c mov   $0f4,a           A:36

da03dc bra $03d9     [da03d9] A:35 H: 590
da03d9 lda $2140     [002140] A:35 H: 608

..096e inc   a                A:36

da03dc bra $03d9     [da03d9] A:36 H: 632
da03d9 lda $2140     [002140] A:36 H: 650

..096f bra   $096c            A:37

da03dc bra $03d9     [da03d9] A:36 H: 674
da03d9 lda $2140     [002140] A:36 H: 692
da03dc bra $03d9     [da03d9] A:36 H: 716
da03d9 lda $2140     [002140] A:36 H: 734

..096c mov   $0f4,a           A:37

da03dc bra $03d9     [da03d9] A:36 H: 758
da03d9 lda $2140     [002140] A:36 H: 776
da03dc bra $03d9     [da03d9] A:36 H: 800
da03d9 lda $2140     [002140] A:36 H: 818

..096e inc   a                A:37

da03dc bra $03d9     [da03d9] A:37 H: 842
da03d9 lda $2140     [002140] A:37 H: 860

..096f bra   $096c            A:38

da03dc bra $03d9     [da03d9] A:37 H: 884
da03d9 lda $2140     [002140] A:37 H: 902
da03dc bra $03d9     [da03d9] A:37 H: 926
da03d9 lda $2140     [002140] A:37 H: 944

..096c mov   $0f4,a           A:38

da03dc bra $03d9     [da03d9] A:37 H: 968
da03d9 lda $2140     [002140] A:37 H: 986
da03dc bra $03d9     [da03d9] A:37 H:1010
da03d9 lda $2140     [002140] A:37 H:1028

..096e inc   a                A:38

da03dc bra $03d9     [da03d9] A:38 H:1052
da03d9 lda $2140     [002140] A:38 H:1070

..096f bra   $096c            A:39

da03dc bra $03d9     [da03d9] A:38 H:1094
da03d9 lda $2140     [002140] A:38 H:1112
da03dc bra $03d9     [da03d9] A:38 H:1136
da03d9 lda $2140     [002140] A:38 H:1154

..096c mov   $0f4,a           A:39

da03dc bra $03d9     [da03d9] A:38 H:1178
da03d9 lda $2140     [002140] A:38 H:1196
da03dc bra $03d9     [da03d9] A:38 H:1220
da03d9 lda $2140     [002140] A:38 H:1238

..096e inc   a                A:39

da03dc bra $03d9     [da03d9] A:39 H:1262
da03d9 lda $2140     [002140] A:39 H:1280

..096f bra   $096c            A:3a

da03dc bra $03d9     [da03d9] A:39 H:1304
da03d9 lda $2140     [002140] A:39 H:1322
da03dc bra $03d9     [da03d9] A:39 H:1346
da03d9 lda $2140     [002140] A:39 H:   0

..096c mov   $0f4,a           A:3a

da03dc bra $03d9     [da03d9] A:39 H:  24
da03d9 lda $2140     [002140] A:39 H:  42
da03dc bra $03d9     [da03d9] A:39 H:  66
da03d9 lda $2140     [002140] A:39 H:  84

..096e inc   a                A:3a

da03dc bra $03d9     [da03d9] A:3a H: 108
da03d9 lda $2140     [002140] A:3a H: 126

..096f bra   $096c            A:3b

da03dc bra $03d9     [da03d9] A:3a H: 150
da03d9 lda $2140     [002140] A:3a H: 168
da03dc bra $03d9     [da03d9] A:3a H: 192
da03d9 lda $2140     [002140] A:3a H: 210

..096c mov   $0f4,a           A:3b

da03dc bra $03d9     [da03d9] A:3a H: 234
da03d9 lda $2140     [002140] A:3a H: 252
da03dc bra $03d9     [da03d9] A:3a H: 276
da03d9 lda $2140     [002140] A:3a H: 294

..096e inc   a                A:3b

da03dc bra $03d9     [da03d9] A:3b H: 318
da03d9 lda $2140     [002140] A:3b H: 336

..096f bra   $096c            A:3c

da03dc bra $03d9     [da03d9] A:3b H: 360
da03d9 lda $2140     [002140] A:3b H: 378
da03dc bra $03d9     [da03d9] A:3b H: 402
da03d9 lda $2140     [002140] A:3b H: 420

..096c mov   $0f4,a           A:3c

da03dc bra $03d9     [da03d9] A:3b H: 444

Could this log help fix Mesen-S? Mesen-S doesn't behave like this.

[Sour]

For maximal programmer/ROM hacker adversity, I'd say it should pick a random rate ±160Hz of nominal on emulation start, and should slowly drift over ±32Hz of that while it's running :P

That doesn't sound too hard really, I'm already recalculating the clock ratio between the CPU & SPC once a frame (in case the region setting is switched), so picking a random +- 32hz value (+ another one at power on) really wouldn't be that hard. Like a lot of stuff Mesen, though, I'd keep this disabled by default and just have it as an advanced option for devs.

d4s' Breath of Fire II (German)

Thanks, I'll keep that in mind for testing (though I just tried using this and couldn't get it to boot in any emulator, but I have a feeling I might just have patched the wrong rom)

There will probably be some conflict if the snes writes data at the same time the SPC initiates a port clear function. Some emulators don't emulate this, BSNES does though.

I'm not too sure about this one? I took a quick look at higan's SPC code, but didn't really see anything that seemed special about the reset? Just seems to sync up to the CPU and then reset the values, which is essentially equivalent to what I have at the moment.

When cpu reads / spc writes to same port simultaneously, bsnes keeps returning old value.

That sounds like it might just be the result of slightly different timing? Not sure. I'll keep it in mind when I get back to trying to fix the SPC. For now I'm half hoping that if I manage to fix whatever is left to fix in terms of timing for DMAs, IRQs and the like, the remaining SPC issues might fix themselves.

[93143]

For maximal programmer/ROM hacker adversity, I'd say it should pick a random rate ±160Hz of nominal on emulation start, and should slowly drift over ±32Hz of that while it's running

That doesn't sound too hard really, I'm already recalculating the clock ratio between the CPU & SPC once a frame (in case the region setting is switched), so picking a random +- 32hz value (+ another one at power on) really wouldn't be that hard.

Ideally the drift would be a bit slower than that.

I'm hoping to eventually get around to testing an advanced HDMA streaming scheme with sync adjustment. My current concept wouldn't work well with rapid timing changes because it only checks the timer ratio once a frame and I'd want to filter the result to smooth out jitter from timer granularity and polling latency.

Also, kicking the timing around that fast might actually be audible...

[lidnariq]

The ±32 Hz (audio rate; APU's CPU rate would be 32 times that) is an upper bound for how bad a ceramic resonator is once it's started running. The problem with just using an ordinary random walk is that it's unbounded.

[93143]

Surely a change that large would take longer than 17 milliseconds? I was under the impression that the signal was pretty regular over the short term, just with thermal drift of the resonant frequency.

[tepples]

Perhaps make the frequency vary with the fraction of cycles that the S-CPU has spent in wai state over the past minute, with some random offset to simulate room temperature.

[klurey]

When cpu reads / spc writes to same port simultaneously, bsnes keeps returning old value.

That sounds like it might just be the result of slightly different timing? Not sure. I'll keep it in mind when I get back to trying to fix the SPC. For now I'm half hoping that if I manage to fix whatever is left to fix in terms of timing for DMAs, IRQs and the like, the remaining SPC issues might fix themselves.

I wrote another test since it could've been coincidence.

Code: Select all

da03df lda $2140     [002140] A:31 H: 972

..0970 mov   $0f4,a           A:32

da03e2 lda $2140     [002140] A:31 H: 996

..0972 mov   $0f4,a           A:33

da03e5 lda $2140     [002140] A:32 H:1020
da03e8 lda $2140     [002140] A:32 H:1044
da03eb lda $2140     [002140] A:32 H:1068

..0974 mov   $0f4,a           A:34

da03ee lda $2140     [002140] A:33 H:1092
da03f1 lda $2140     [002140] A:33 H:1116
da03f4 lda $2140     [002140] A:33 H:1140
da03f7 lda $2140     [002140] A:33 H:1164

..0976 mov   $0f4,a           A:35

da03fa lda $2140     [002140] A:34 H:1188
da03fd lda $2140     [002140] A:34 H:1212
da0400 lda $2140     [002140] A:34 H:1236

..0978 mov   $0f4,a           A:36

da0403 lda $2140     [002140] A:35 H:1260
da0406 lda $2140     [002140] A:35 H:1284
da0409 lda $2140     [002140] A:35 H:1308
da040c lda $2140     [002140] A:35 H:1332

..097a mov   $0f4,a           A:37

da040f lda $2140     [002140] A:36 H:1356
da0412 lda $2140     [002140] A:36 H:  16
da0415 lda $2140     [002140] A:36 H:  40

..097c mov   $0f4,a           A:38

da0418 lda $2140     [002140] A:37 H:  64
da041b lda $2140     [002140] A:37 H:  88
da041e lda $2140     [002140] A:37 H: 112
da0421 lda $2140     [002140] A:37 H: 136

..097e mov   $0f4,a           A:39

da0424 lda $2140     [002140] A:38 H: 160
da0427 lda $2140     [002140] A:38 H: 184
da042a lda $2140     [002140] A:38 H: 208

..0980 mov   $0f4,a           A:3a

da042d lda $2140     [002140] A:39 H: 232

Bsnes always 1 step behind like before. Regardless of 1,3,4 cpu opcodes between each spc opcode.

[klurey]

Does libretro port have input problem? Joypad1 uses both retropads: Retropad1 (A,X,Y,L,R) + Retropad2 (D-Pad,Start,Select,B)

[Sour]

Does libretro port have input problem? Joypad1 uses both retropads: Retropad1 (A,X,Y,L,R) + Retropad2 (D-Pad,Start,Select,B)

It seems to be working fine as far as I can tell? I've reset my retroarch configuration to be sure and it seems to be binding the correct buttons.

[lidnariq]

Surely a change that large would take longer than 17 milliseconds? I was under the impression that the signal was pretty regular over the short term, just with thermal drift of the resonant frequency.

I wasn't suggesting that ±32Hz per vsync was reasonable... I was stating that it should never deflect more than ±32Hz from whatever frequency it started with.

In practice, ceramic resonator drift does seem to be mostly thermal, and in turn that appears to usually be a positive monotonic coefficient among higher-frequency resonators.

But from the point of view of simulating an plausibly adverse environment, it probably shouldn't only model the thermal coefficient. A random walk, as long as it's slow enough and bounded, is probably more useful.

[klurey]

Does libretro port have input problem? Joypad1 uses both retropads: Retropad1 (A,X,Y,L,R) + Retropad2 (D-Pad,Start,Select,B)

It seems to be working fine as far as I can tell? I've reset my retroarch configuration to be sure and it seems to be binding the correct buttons.

It seems to be some msvc2017 msbuild optimization problem (libretro|x86).

This does that wonky retropad1+2 reading:

Code: Select all

		case 0x4219: case 0x421B: case 0x421D: case 0x421F:
			return (uint8_t)(_controllerData[((addr & 0x0E) - 8) >> 1] >> 8);

And this behaves like expected:

Code: Select all

		case 0x4219: case 0x421B: case 0x421D: case 0x421F:
			printf("%04x: %04x %04x %04x = %04x %04x %04xn",
				addr,
				(addr & 0x0E), (addr & 0x0E) - 8, ((addr & 0x0E) - 8) >> 1,
				_controllerData[((addr & 0x0E) - 8) >> 1], _controllerData[((addr & 0x0E) - 8) >> 1] >> 8,
				(uint8_t) (_controllerData[((addr & 0x0E) - 8) >> 1] >> 8)
				);

			return (uint8_t)(_controllerData[((addr & 0x0E) - 8) >> 1] >> 8);

Using unmodified git source in both cases. And for libretro.cpp, I can't see core options unless I switch from

Code: Select all

static const char* ==> static constexpr char*

I guess both are somehow unique to me. But that last one is more confusing.

Building latest Retroarch git using msvc2017 project. I'll try mingw building also to see what happens.

[Sour]

A random walk, as long as it's slow enough and bounded, is probably more useful.

Could probably just do something like +1 per X seconds, until you hit -32, then -1 per X seconds until you hit -32, or something akin.

And this behaves like expected:

So you're saying adding a printf statement fixes the problem? That's never a good sign... FYI I have not tested the 32-bit builds of Mesen-S at all (libretro or not) - the way I setup the configuration between the UI and the core doesn't like the 32-bit builds, and I haven't had the time to either find a solution or implement a workaround. That being said, I don't see why this would fail in x86 but not x64...

I can't see core options unless I switch from

That's my fault - it was an issue on the Mesen core in some configurations too (originally the person said Windows XP, but maybe it's more of a 32-bit issue?), but I forgot to bring over that fix when I made the libretro build of Mesen-S. I've fixed the code - thanks for letting me know.