HuC6201 64-pin QFP, 19x13, 1mm pin spacing
Code: Select all
no diode -- / 1 .
no diode -- / 2 \
RAM /OE <- / 3 \ \
RAM /WE <- / 4 /\ \/\
*RAM /CE <- / 5 \ \ \ \
CPU A18 -> / 6 /\ \ \
HSM ?> / 7 \
CPU A9 -> / 8 /\ \
CPU /WR -> / 9 \ \ \
CPU A17 -> / 10 /| \/\ /
CPU A14 -> / 11 / | |
CPU A13 -> / 12 | /
CPU A8 -> / 13 /\ | \
/LED1 <- / 14 / \ \_/
/LED2 <- / 15 \ \
/LED3 <- / 16 \ \ \
no diode -- / 17 \ \ /
no diode -- / 18 \ \/
batterygood -> / 19 O \
CPU A11 -> \ 20
CPU /RD -> \ 21
CPU D0 <> \ 22
CPU D2 <> \ 23
CPU D3 <> \ 24
+5V -- \ 25
Gnd -- \ 26
CPU D4 <> \ 27
CPU D5 <> \ 28
CPU D6 <> \ 29
no diode -- \ 30
CPU A10 -> \ 31
CPU D7 <> \ 32
64\ <> RAM D7
63\ <> RAM D6
62\ -- no diode
61\ <> RAM D5
60\ <> RAM D4
59\ <> RAM D3
58\ -- Gnd
57\ ?? diode??
56\ <> RAM D2
55\ <> RAM D1
54\ <> RAM D0
53\ -> RAM A0
O 52\ -> RAM A1
51/ <- /RESET
50/ -- no diode
49/ -- no diode
48/ <- CPU A20
47/ <- CPU A19
46/ <- CPU A16
45/ <- CPU A15
44/ <- CPU A12
43/ <- CPU A7
42/ <- CPU A6
41/ <- CPU A5
40/ <- CPU A4
39/ <> CPU D1
38/ <- CPU A3
37/ <- CPU A2
36/ <- CPU A1
35/ <- CPU A0
34/ -- no diode
33/ -- no diode
There's several minor interesting things here:
1- There are three pins connected to the LED, but the load resistor for the LED is 560 ohms, and I measured 3V across that resistor, or 5.4mA. One doesn't usually need so many pins for so little current.
2- The data bus, A0, and A1 are relayed through the HuC6201, but not A2 and A3. The 2KB (16kibit) SRAM is most likely a square array of 27 bits on a side, so if this was some kind of magic to minimize power consumption by blocking changes in the column selector stage, it should need more address lines.
3- Although there's a bunch of pins that were just never needed (presumably no wire bond, I could measure no diode from ground or to +5V), there's one pin (# 57) that has over- and under- voltage diodes but isn't connected to anything else on the board. I wonder what it is?
* Pin 5 ("RAM /CE") goes through an external pass transistor, enabled by a voltage threshold IC, before actually connecting to the RAM's /CE input.
This seems needlessly complicated for something that should only have needed access to A20 through A11, but maybe NEC had lots of spare capacity on this one packaging line.
(This was my 10000th post according to the forum's count.)