Apologies for necrobumping, but I'm haunted by one of the most stupid questions that also happens to be related to the answer(s) to OP.
Is it known which of 2A03 register accesses can be observed from outside the chip?
In particular, could a cartridge directly snoop on $4016 and $4017 reads, including ones doubled by the DPCM glitch?
For standard controller reading, baking that into a cart would be an absolute overkill, but, one, I'm just curious, two, it could be worth it for programs using those ports a lot, e.g. for floppies or something.
A question about CPU address exposed to the cartridge
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Re: A question about CPU address exposed to the cartridge
Yes. External hardware can snoop on everything except reads from $4015.
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Re: A question about CPU address exposed to the cartridge
Thank you, that was quick. I didn't expect one to be different from the others. Now that I've read your reply, I guess this property of $4015 is mentioned on the wiki, but in a way that doesn't make it obvious it doesn't apply to other ones, especially in context of this thread ("internal to the CPU").
Now, how to rephrase it...
Now, how to rephrase it...
Re: A question about CPU address exposed to the cartridge
Mind mentioning what page on the wiki so that I could try to figure out how to rephrase it to make that clear?
Re: A question about CPU address exposed to the cartridge
He's likely referring to this bullet point here: "This register is internal to the CPU and so the external CPU data bus is disconnected when reading it. Therefore the returned value cannot be seen by external devices and the value does not affect open bus."
While there's probably no harm in calling out here that this is the only such place on the system where this happens, I'm not sure it's the right place. I think my best suggestion for that right now is CPU memory map. I think the default assumption should be that everything is visible on the bus. Since joypad reads are coming from the joypads, I also think it's reasonable to assume those might be using the bus as normal, meaning $4015 is the only readable CPU address that is coming from a place internal to the CPU.
While there's probably no harm in calling out here that this is the only such place on the system where this happens, I'm not sure it's the right place. I think my best suggestion for that right now is CPU memory map. I think the default assumption should be that everything is visible on the bus. Since joypad reads are coming from the joypads, I also think it's reasonable to assume those might be using the bus as normal, meaning $4015 is the only readable CPU address that is coming from a place internal to the CPU.
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Re: A question about CPU address exposed to the cartridge
Coming from the SNES, I'd assume the NES joypads have dedicated lines going to/from the CPU...
My current setup:
Super Famicom ("2/1/3" SNS-CPU-GPM-02) → SCART → OSSC → StarTech USB3HDCAP → AmaRecTV 3.10
Super Famicom ("2/1/3" SNS-CPU-GPM-02) → SCART → OSSC → StarTech USB3HDCAP → AmaRecTV 3.10
Re: A question about CPU address exposed to the cartridge
On the NES, the output-to-joypad path uses special pins (OUT0, OUT1, OUT2, joypad 1 /OE, joypad 2 /OE), while the input-from-joypad path just uses the bus as normal.
(Speaking of which, on SNES, we currently say on the wiki that the upper bits for joypad reads are open bus, but I'm wondering if that's external open bus or internal open bus. And more generally, does reading from a 5A22 register have the same behavior as reading from $4015 where it isolates the CPU's internal bus from the external bus? If anyone knows, please message me the answer so I can update the wiki.)
(Speaking of which, on SNES, we currently say on the wiki that the upper bits for joypad reads are open bus, but I'm wondering if that's external open bus or internal open bus. And more generally, does reading from a 5A22 register have the same behavior as reading from $4015 where it isolates the CPU's internal bus from the external bus? If anyone knows, please message me the answer so I can update the wiki.)
Re: A question about CPU address exposed to the cartridge
Isn't that a function of save state?
Almost all registers, internal workram, ciram, external workram, pattern table, palette, and so on...
However, the PC cannot be restored, that's not important. After entering the interrupt through nmi, it will be resynchronized