Code: Select all
always@(posedge m2) begin
if(nesprg_we) begin
casex({ain[15:12],ain[1:0]})
6'b1000xx:prgbank8<=nesprgdin; //800x
6'b1100xx:prgbankC<=nesprgdin; //C00x
6'b101111:mirror<=nesprgdin[3:2]; //B003
6'b110100:chrbank0<=nesprgdin; //D000
6'b110101:chrbank1<=nesprgdin; //D001
6'b110110:chrbank2<=nesprgdin; //D002
6'b110111:chrbank3<=nesprgdin; //D003
6'b111000:chrbank4<=nesprgdin; //E000
6'b111001:chrbank5<=nesprgdin; //E001
6'b111010:chrbank6<=nesprgdin; //E002
6'b111011:chrbank7<=nesprgdin; //E003
6'b111100:irqlatch<=nesprgdin; //F000
6'b111101:{irqM,irqA}<={nesprgdin[2],nesprgdin[0]}; //F001
endcase
end
end
m2 seems to come straight from the console and ain[15] is just the inverted version of /ROMSEL:
Code: Select all
IBUFG b01(.I(NES_M2),.O(m2));
...
IBUF b20(.I(NES_PRG_CE),.O(nesprg_ce));
assign prgain[15]=!nesprg_ce;
So, my question is: how are these mappers able to function at all? Does the PowerPak introduce some delay to M2 external to the FPGA?