Becoming an FPGA Engineer

You can talk about almost anything that you want to on this board.

Moderator: Moderators

User avatar
Ben Boldt
Posts: 1149
Joined: Tue Mar 22, 2016 8:27 pm
Location: Minnesota, USA

Becoming an FPGA Engineer

Post by Ben Boldt »

I never thought it would happen, but in the coming months I may find myself presented with an opportunity to switch over from a regular firmware engineer (microcontrollers) to FPGA engineer. I haven't touched an FPGA since about 11-12 years ago when I took a class in college, so I am very rusty, to the point of almost square 1. I know that the job would entail using VHDL and cost constraints won't be a huge concern. I don't know much more than that.

I am wondering if anyone has recommendations for some good tutorials and demo boards that I could work my way through in the meantime. I tend to do a bit better with a book for these sorts of things, 'for dummies' style guides have always been a favorite of mine. (I'm definitely a dummy at this point.) I figure I should ask for guidance here since ultimately you're why I want to build those skills.
lidnariq
Posts: 11432
Joined: Sun Apr 13, 2008 11:12 am

Re: Becoming an FPGA Engineer

Post by lidnariq »

My understanding is that basically all the existing test stuff sucks. Sucks to define, sucks to test, slow as molasses on a winter day. Hence grotesque hacks like viewtopic.php?t=18737

I recently did a project that required dusting off my college-era VHDL learning Verilog and discovered that "blinking LED" debugging hurt less.
Garth
Posts: 246
Joined: Wed Nov 30, 2016 4:45 pm
Location: Southern California
Contact:

Re: Becoming an FPGA Engineer

Post by Garth »

I started getting into programmable logic (CPLDs though, not FPGAs) in the late 1990's, and Cypress had books and software which I think was free because they wanted us to design their parts into our products. It has been over 20 years; but you might see what they're offering now. The one project I was working on that was going to use the CPLD got cancelled before I was finished, but it was not hard to get as far as I did which was write, simulate, and synthesize. I was stopped just as I was about to start programming and trying parts. If I were to take it up again now, I'd have to start over, since I didn't get enough experience to make it stick.
http://WilsonMinesCo.com/ lots of 6502 resources
calima
Posts: 1745
Joined: Tue Oct 06, 2015 10:16 am

Re: Becoming an FPGA Engineer

Post by calima »

AFAIK there's only one model that has an open source toolchain, so if at all possible, you should target that. Otherwise you're stuck with one vendor's whims and programs, that may change, become deprecated, and with experience that doesn't transfer well to any other vendor.
lidnariq
Posts: 11432
Joined: Sun Apr 13, 2008 11:12 am

Re: Becoming an FPGA Engineer

Post by lidnariq »

Unfortunately, the IceStorm system is ... just not that good. I mean, it's fine, in the sense that it's the only meaningfully open-source one, but it produces fusemaps that are measurably inferior (both speed and area efficiency).

You're unlikely to be meaningfully able to pick to use only the YOSyS toolchain.
User avatar
Bregalad
Posts: 8056
Joined: Fri Nov 12, 2004 2:49 pm
Location: Divonne-les-bains, France

Re: Becoming an FPGA Engineer

Post by Bregalad »

calima wrote: Tue May 25, 2021 12:01 am AFAIK there's only one model that has an open source toolchain, so if at all possible, you should target that. Otherwise you're stuck with one vendor's whims and programs, that may change, become deprecated, and with experience that doesn't transfer well to any other vendor.
I can't say for now but 2 years ago (so in 2019) the free software possibilities were virtually nonexistant for FPGA. Not only you need to compile your HDL description (VHDL or Verilog) with a free software but you also have to map/route it to your FPGA with free software and also program your board with free software. Although some attemps have been made with some Lattice boards, the available tools won't work except with a very particular board from Lattice, and that very particular board had so few I/Os I didn't get the point of choosing it.

In summary, FPGA development is essentially proprietary for the time being and for a foreseeable future.
Useless, lumbering half-wits don't scare us.
lidnariq
Posts: 11432
Joined: Sun Apr 13, 2008 11:12 am

Re: Becoming an FPGA Engineer

Post by lidnariq »

Bregalad wrote: Tue May 25, 2021 2:48 am Although some attemps have been made with some Lattice boards, the available tools won't work except with a very particular board from Lattice, and that very particular board had so few I/Os I didn't get the point of choosing it.
That's .... not true at all.

The full iCE40HX, iCE40LP, and iCE40UP lines are all supported, and all you need to program the board is to program the generated fusemap into the 25xxx series SPI flash on the board.
User avatar
Ben Boldt
Posts: 1149
Joined: Tue Mar 22, 2016 8:27 pm
Location: Minnesota, USA

Re: Becoming an FPGA Engineer

Post by Ben Boldt »

I think that I will create a setup with a Famicom, level-shifting everything in the cartridge connector, connecting 3.3V ROMs and RAMs, and program a CPLD to reproduce mappers of increasing complexity.
  1. Take CPLD out of the picture, ground all upper address bits, program ROMs with an NROM game. Just to verify the setup.
  2. Same thing but control the grounded signals with the CPLD, setting those pins statically low. That's a pretty good 'hello world' to just set output low, hopefully I can figure that out.
  3. Mapper 7 (AxROM), (1 register), program the ROMs with such a game
  4. Mapper 2 (UxROM), (1 register, 1 multiplexer)
  5. VRC1
  6. MMC1
    etc.
Just a step at a time getting more and more complex as a way to refresh and learn the skills needed for whatever might be coming. I have been thinking that maybe replacing an SRAM (CHR-RAM or PRG-RAM) with a DRAM would be an interesting challenge as well.
User avatar
Ben Boldt
Posts: 1149
Joined: Tue Mar 22, 2016 8:27 pm
Location: Minnesota, USA

Re: Becoming an FPGA Engineer

Post by Ben Boldt »

Does this look correct for using 74LVC245 level shifting bus transceivers:
level_shifters.png
I am wondering if the AND gate for /OE is correct on the right/center chip for the PPU data bus. (I don't think I have to do anything like that on the CPU data bus.) Also I am wondering what value resistors to use. I want those resistors in case I screw something up and drive 2 outputs together, as I do expect to stumble a lot working with this thing. I was thinking 100 ohms for all of those, but not sure if maybe it should be lower than that.

When DIR = 0, the direction is B->A (leftwards) I have all chips set in this mode except the data busses. I have not started building this yet so I am very open to any ideas to do the whole thing different/better.
lidnariq
Posts: 11432
Joined: Sun Apr 13, 2008 11:12 am

Re: Becoming an FPGA Engineer

Post by lidnariq »

Ben Boldt wrote: Wed May 26, 2021 11:34 am Does this look correct for using 74LVC245 level shifting bus transceivers:
Looks right?
I am wondering if the AND gate for /OE is correct on the right/center chip for the PPU data bus. (I don't think I have to do anything like that on the CPU data bus.)
It's not wrong to say that the PPU's data bus is always an output except when /RD is asserted, the same logic as what's inside the PPU.
Also I am wondering what value resistors to use. I want those resistors in case I screw something up and drive 2 outputs together, as I do expect to stumble a lot working with this thing. I was thinking 100 ohms for all of those, but not sure if maybe it should be lower than that.
I don't think I can help here, unfortunately. I suspect the big thing is probably PCB layout to minimize odds of accidentally shorting things.
User avatar
Ben Boldt
Posts: 1149
Joined: Tue Mar 22, 2016 8:27 pm
Location: Minnesota, USA

Re: Becoming an FPGA Engineer

Post by Ben Boldt »

lidnariq wrote: Wed May 26, 2021 12:20 pm
Ben Boldt wrote: Wed May 26, 2021 11:34 am I am wondering if the AND gate for /OE is correct on the right/center chip for the PPU data bus. (I don't think I have to do anything like that on the CPU data bus.)
It's not wrong to say that the PPU's data bus is always an output except when /RD is asserted, the same logic as what's inside the PPU.
Are you saying I should be OK to set /OE to 0 and control DIR with just PPU /RD and swap sides for everything like this:
ppu_data_bus.png
lidnariq wrote:
Ben Boldt wrote:Also I am wondering what value resistors to use. I want those resistors in case I screw something up and drive 2 outputs together, as I do expect to stumble a lot working with this thing. I was thinking 100 ohms for all of those, but not sure if maybe it should be lower than that.
I don't think I can help here, unfortunately. I suspect the big thing is probably PCB layout to minimize odds of accidentally shorting things.
I had planned to just wire it all with breadboards and use directly a CPLD demo board. I don't plan to make something insertable as a cartridge or anything like that, just strictly doing everything as a learning tool.
lidnariq
Posts: 11432
Joined: Sun Apr 13, 2008 11:12 am

Re: Becoming an FPGA Engineer

Post by lidnariq »

Ben Boldt wrote: Wed May 26, 2021 4:44 pm Are you saying I should be OK to set /OE to 0 and control DIR with just PPU /RD and swap sides for everything like this:
It's a little uncomfortable because of propagation delay, but ... I find it credible?

On the other hand, I think your original design was fine too, and doesn't obviously have propagation delay problems (because the '245 is always Hi-Z before and after each read or write)
User avatar
Ben Boldt
Posts: 1149
Joined: Tue Mar 22, 2016 8:27 pm
Location: Minnesota, USA

Re: Becoming an FPGA Engineer

Post by Ben Boldt »

I actually have some tiny 74LVC1G08 (single 2-input AND gate) chips. I might use the newer drawing (PPU /RD controlling DIR) except throw (PPU /RD AND PPU /WR) into /OE. Couldn't hurt I guess.

I was thinking of using a front-loader, removing the ZIF connector, and attaching a famiclone female edge connector directly on the motherboard. Then set a piece of plastic or wood on top of the motherboard where I can put various breadboards. First running the whole cartridge connector through these level shifters, then to the 3.3V memories and CPLD.

This might be pretty fun! I will try to share it in a meaningful way in case anyone else wants to use a Nintendo to start from square 1 with learning CPLDs. Also in case anyone is nice enough to correct my errors!

A guy at work gave me a few demo boards. This one is the simpler of them and I might start there:

https://www.intel.com/content/www/us/en ... max-v.html

I also have one of those AliExpress EPM240 breakout boards with USB blaster that I have played with before but I figured I better start with a real demo board.
Pokun
Posts: 2681
Joined: Tue May 28, 2013 5:49 am
Location: Hokkaido, Japan

Re: Becoming an FPGA Engineer

Post by Pokun »

Please do share, I started to slowly learn some basic programmable logic some time ago, and am very interested in your progress if you don't mind. :)


Before Pickit 2 there wasn't any easy way for artists to get into microcontrollers, and now we have plug-'n-play options like Arduino. PLD/FPGA is still in its infant stages but now low-cost development boards like the iCEstick at least exists for hobbyists to start with, so I guess it's getting there sooner or later.
User avatar
Ben Boldt
Posts: 1149
Joined: Tue Mar 22, 2016 8:27 pm
Location: Minnesota, USA

Re: Becoming an FPGA Engineer

Post by Ben Boldt »

Just getting started with the physical setup. I have some sockets and pin headers laid out and also a lovely piece of plywood to attach things. I have to bring in some standoffs I have at home. I will be running millions of wires soon. Like I said before, goal #1 is just shorting those various pins on the bottom to get an NROM game running without the CPLD even in the picture yet.
cpld_setup.jpg
pinout.jpg
Post Reply