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.--\/--.
M2 -> |01 40| -- VCC
CPU R/W -> |02 39| <- PPU A10
/ROMSEL -> |03 38| <- PPU A11
WRAM +CE <- |04 37| <- PPU A12
WRAM /CE <- |05 36| <- CPU A0
WRAM /WE <- |06 35| <- CPU A13
PRG /CE <- |07 34| <- CPU A14
CPU D0 -> |08 33| -> /IRQ
CPU D1 -> |09 32| -> DELAYED M2
CPU D2 -> |10 31| -> CIR A10
CPU D3 -> |11 30| -> CHR A17
CPU D4 -> |12 29| -> CHR A15
CPU D5 -> |13 28| -> CHR A14
CPU D6 -> |14 27| -> CHR A13
CPU D7 -> |15 26| -> CHR A12
PRG A13 <- |16 25| -> CHR A11
PRG A14 <- |17 24| -> CHR A10
PRG A15 <- |18 23| -> CHR A16
PRG A16 <- |19 22| -> PRG A18
GND -- |20 21| -> PRG A17
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T1
* Pins 4 and 5 are normally disabled (pin4 = 0, pin5 = 1). They are asserted (pin4 = 1, pin5 = 0):
- during read cycle from $6000-$7fff when $A001.7=1
- during write cycle to $6000-$7fff when $A001.7=1 and $A001.6=0
* Pins 4 and 5 are asserted 110ns after M2 goes up and deasserted 20ns after M2 goes down
* Pin 6 is asserted around 180ns after M2 goes up and deasserted 20ns after M2 goes down
* There does not seem to be any consistent power-up value for the $a001
* Pin 6 is low when when R/W=0 and M2=1, no matter what $A001 is
* Pin 32 goes up 100ns after M2 goes up and goes down 80ns after M2 goes down