Sunsoft 5B pin 18

Discuss hardware-related topics, such as development cartridges, CopyNES, PowerPak, EPROMs, or whatever.

Moderator: Moderators

Post Reply
User avatar
krzysiobal
Posts: 1037
Joined: Sun Jun 12, 2011 12:06 pm
Location: Poland
Contact:

Sunsoft 5B pin 18

Post by krzysiobal »

I've just discovered that in Sunsoft 5B this pin is an input (pulled high internally). Not connected to anything at least in the GRM-E301 pcb.

I've send those commands to the chip to generate a square wave for channel A of period 256 (contant M2 clocking with 2 MHz is turned on)

Code: Select all

CPU W 00 C000
CPU W 00 E000
CPU W 01 C000
CPU W 01 E000 
CPU W 08 C000
CPU W 0F E000
CPU W 09 C000
CPU W 00 E000
CPU W 0A C000
CPU W 00 E000
CPU W 07 C000
CPU W FE E000
And so I got expected 2 MHz / (32 * 256) = 244 Hz square wave:
pin18=1.png
Then pulled this pin low and the sqare wave frequency doubled:
pin18=0.png

When I tried to send next commands when this pin is low, they were completely ignored.
And when this pin is held low from the very beginning and then I ran the above code, I don't get square wave at all.
And when I run Gimmick game with this pin held low, there is a weird cracking noise instead of external audio.

So my guess is that this pin is somewhat related to the /SEL pin in YM2149.

Changing values of this pin does not alter the functionality of pins 1/2 - they're still behaveing like AMP-IN and AMP-OUT.
Pokun
Posts: 2681
Joined: Tue May 28, 2013 5:49 am
Location: Hokkaido, Japan

Re: Sunsoft 5B pin 18

Post by Pokun »

Interesting, so the /SEL pin is actually available on the Sunsoft 5b in a way.
The wiki says that the Sunsoft 5B operates as a YM2159F with the /SEL pin tied low, which means the input clock is divided by 2. But this pin seems to have the opposite effect when activated and doubles the input clock instead (or I guess it technically backs off from halving the clock internally when this pin is low).
User avatar
rainwarrior
Posts: 8732
Joined: Sun Jan 22, 2012 12:03 pm
Location: Canada
Contact:

Re: Sunsoft 5B pin 18

Post by rainwarrior »

My assumption was that low-SEL on a YM2419 "halves" the clock to permit the 32-step envelopes rather than the 16-step anvelopes of the AY. I haven't yet tested a real YM2149 chip to verify this though. The datasheet description just seems that SEL floating / high = AY compatibility mode.

This behaviour seems like SEL's description but inverted?

You might try using a slow envelope and counting the steps with it high and low.
Pokun
Posts: 2681
Joined: Tue May 28, 2013 5:49 am
Location: Hokkaido, Japan

Re: Sunsoft 5B pin 18

Post by Pokun »

Yeah seems the same as SEL but inverted, that's what I tried to say.

One point for the YM2419F to have SEL floating/high for AY compatibility is that this pin should normally be high in a setup that uses the AY, so this design makes it a drop-in replacement for the AY (aside from the higher envelope resolution and other smaller differences).
I think some MSX computers that uses the YM2419F as PSG feeds it a 3.579545 MHz clock (double the normal MSX PSG clock) and ties the SEL pin low to halve it to normal MSX PSG speed. Maybe this is for halving the envelope resolution to improve compliance with the MSX standard (which defines the AY-3-8910 as PSG) like you theorized.
lidnariq
Posts: 11432
Joined: Sun Apr 13, 2008 11:12 am

Re: Sunsoft 5B pin 18

Post by lidnariq »

Yeah, it sounds like inverted SEL, except that:
krzysiobal wrote: Sat May 29, 2021 7:47 am When I tried to send next commands when this pin is low, they were completely ignored.
Pokun
Posts: 2681
Joined: Tue May 28, 2013 5:49 am
Location: Hokkaido, Japan

Re: Sunsoft 5B pin 18

Post by Pokun »

What does that mean? It only work for a while then starts ignoring input?
lidnariq
Posts: 11432
Joined: Sun Apr 13, 2008 11:12 am

Re: Sunsoft 5B pin 18

Post by lidnariq »

The input does more than just change the divider: it also prevents further updates to the sound hardware. (Untested: it might also prevent updates to other mapper registers)
Pokun
Posts: 2681
Joined: Tue May 28, 2013 5:49 am
Location: Hokkaido, Japan

Re: Sunsoft 5B pin 18

Post by Pokun »

I see, so it's not simply an inverted SEL pin.
User avatar
krzysiobal
Posts: 1037
Joined: Sun Jun 12, 2011 12:06 pm
Location: Poland
Contact:

Re: Sunsoft 5B pin 18

Post by krzysiobal »

Here is my summary of what is my observations:
* this pin does not change behavior of PRG/CHR/IRQ functionality at all (Gimmick work fine with its being low, just external audio is not audible)
* when this pin is LOW, any writes to $e000 does not have any effect
* any writes to $c000 when this pin is LOW do not change currently set register that will be updated when writing to $e000 when pin 18 is high
* when CPU A14 = 1 and CPU A13 = 0 and this pin becomes low, the value of register at $e000 is set to $ff
* any audio wave, if generated, increases its frequency twice when this pin becomes LOW and returns to decreased frequency when it becomes HIGH again.
* Wiki says that the audio register select at $c000 is 4 bit. In fact, it pays attention to all eight bits (when a register is set from $10 to $ff, any write to $e000 is ignored)

So my thoughts are that this pin is in fact not related to the SEL at all, but this is is just some kind of reset pin.
Why the audio frequency increases then? My guess is that the clock divider inside the chip, when this pin is LOW, also stays in reset and stops division. No idea how the divider is implemented then.
Post Reply