Oh cool thanks for the quick turn around on the test ROM. It seems my diagnosis was correct. Not sure how it manages to be off by 2 cycles though, I guess the counter changes at a different point then I thought.
Pretty incredible that no other game I had previous tested ran into this case. Or maybe reading from the status register isn't that common.
Anyway thanks again!
Count Errors Test ROM and some new DMC glitch info
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Re: Count Errors Test ROM and some new DMC glitch info
Oh this is awesome. Just wanted to share appreciation to you both for the investigation and test case. Also I'm kind of excited because mine apparently does the right thing! Adding to the round of tests. Seriously this whole topic is golden.
Re: Count Errors Test ROM and some new DMC glitch info
Alyosha: I've put all of my DMA knowledge up on the wiki here. I'd really appreciate if you could take a look at this and verify it matches your understanding, since I think you're currently the only other person here who understands this topic all that well!
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- Posts: 173
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Re: Count Errors Test ROM and some new DMC glitch info
Yes what you have there looks like it matches what I have in my code / notes. I think the only thing that is missing is that if the DMC DMA occurs on the APU cycle before the buffer would be emptied (0 bits remaining in the sample, but non-zero samples remaining) then there will not be another DMC DMA triggered. In other words the currently playing sample and the buffer will both still be considered filled.
I can't remember what game or test this case occurred in though.
Aside from that there are still a lot of IRQ details, but honestly I'm not sure how well I could even explain it myself anymore.
I can't remember what game or test this case occurred in though.
Aside from that there are still a lot of IRQ details, but honestly I'm not sure how well I could even explain it myself anymore.
Re: Count Errors Test ROM and some new DMC glitch info
Allow me to break in to you.
We now have the ability to test APU circuits using the HDL implementation on Verilog:
Test Bench can be found here:
https://github.com/emu-russia/breaks/tr ... Icarus/apu
For testing OAM DMA and DPCM DMA see oam_dma.bat and both_dma.bat
Results are as follows:
- ACLK and PHI alignment mismatch is related to /RES signal duration
- The extra delay cycle of non-aligned OAM DMA is due to the fact that the latch where DMA start events are stored is enabled only at #ACLK ("Unaligned OAM DMA" case)
- DPCM DMA contains additional delay cycles on purpose. This is done for the reason that if DPCM DMA and OAM DMA intersect - DPCM DMA cannot immediately start doing reads (simultaneously with OAM DMA). So the circuit purposefully waits for 2 cycles and gives the OAM DMA hold signal, then does its own reading and an additional empty cycle instead of writing $2004 (marked as "resume" or "bogus" in the diagrams). ("Dummy DPCM DMA Cycles" case)
Attached are .vcd files for GTKWave for those who like to look into such things.
You can also check how the circuits work using Logisim 3.8.0:
https://github.com/emu-russia/breaks/bl ... k_Evo.circ
That's enough for now
We now have the ability to test APU circuits using the HDL implementation on Verilog:
Test Bench can be found here:
https://github.com/emu-russia/breaks/tr ... Icarus/apu
For testing OAM DMA and DPCM DMA see oam_dma.bat and both_dma.bat
Results are as follows:
- ACLK and PHI alignment mismatch is related to /RES signal duration
- The extra delay cycle of non-aligned OAM DMA is due to the fact that the latch where DMA start events are stored is enabled only at #ACLK ("Unaligned OAM DMA" case)
- DPCM DMA contains additional delay cycles on purpose. This is done for the reason that if DPCM DMA and OAM DMA intersect - DPCM DMA cannot immediately start doing reads (simultaneously with OAM DMA). So the circuit purposefully waits for 2 cycles and gives the OAM DMA hold signal, then does its own reading and an additional empty cycle instead of writing $2004 (marked as "resume" or "bogus" in the diagrams). ("Dummy DPCM DMA Cycles" case)
Attached are .vcd files for GTKWave for those who like to look into such things.
You can also check how the circuits work using Logisim 3.8.0:
https://github.com/emu-russia/breaks/bl ... k_Evo.circ
That's enough for now
- Attachments
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- oam_dma.zip
- (656.74 KiB) Downloaded 24 times
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- both_dma.zip
- (1.03 MiB) Downloaded 25 times
Re: Count Errors Test ROM and some new DMC glitch info
Fiskbit's test ROMs on the Dendy-like chipset
1) UMC UA6527P + UMC UA6538
2) TA-03NP1 (6527P) + TA-02NP (6538)
apu_register_activation_test_wip1
dmc_dma_implicit_stop_test_wip1
dmc_dma_explicit_stop_test_wip1
dmc_dma_status_test_wip1
1) UMC UA6527P + UMC UA6538
2) TA-03NP1 (6527P) + TA-02NP (6538)
apu_register_activation_test_wip1
dmc_dma_implicit_stop_test_wip1
dmc_dma_explicit_stop_test_wip1
dmc_dma_status_test_wip1
- Attachments
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- DMC_6527P_6538.7z
- (208.66 KiB) Downloaded 29 times