stretching the Super FX

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93143
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stretching the Super FX

Post by 93143 »

I've already proposed messing with the oscillator and internal clock divider settings to produce a 21.4 MHz Super FX that accesses its memory buses in three cycles per byte instead of five.

Now I have a couple of questions about the ROM.

First, are we really sure that the GSU2 is physically limited to 2 MB? There was some talk a long while back that suggested it might not be, and fullsnes still describes pin 21 as ? (NC, probably /CE for 2nd ROM chip), which sounds like it could be effectively A21. There's even room in the official SNES-side memory map for 4 MB, although half of it is a mirror of the other half.

Second, what if some or all of the Super FX ROM were actually SRAM, and the cartridge were set up to allow the S-CPU to write to it? (I guess if all of it were SRAM you'd have to mirror at least some of the first bank of CPU ROM to bank $00 so the S-CPU would boot. And if it were 4 MB, doing this would prevent the S-CPU from reading that part of the SRAM because it wouldn't be mirrored anywhere, although you should still be able to write to it...)
calima
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Re: stretching the Super FX

Post by calima »

2mb SRAM would be really expensive.
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Nikku4211
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Re: stretching the Super FX

Post by Nikku4211 »

These are some cool what ifs, I can't wait until someone who has an SMW2 or SNES Doom cartridge decides to take out the GSU-2 chip and make a test cart with it to flash and test on.
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93143
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Re: stretching the Super FX

Post by 93143 »

calima wrote: Fri Apr 15, 2022 12:23 am2mb SRAM would be really expensive.
What, today? I know it would be expensive in 1996; it's 8 times the total amount of SRAM in the maximal official configuration, which no one used, and the clock trick requires 120 ns memory. Anyway, the MSU1 that would be necessary to take full advantage of this would be worse.

How would 2 MB of SRAM compare with the ST-018?

I suppose one could use DRAM, but that opens up a whole other technical can of worms (as well as stealing GSU compute time for refresh)...

...

The part that makes this idea an actual question rather than just a what-if is the fact that the ROM is supposed to be 100% controlled by the Super FX, which quite understandably has no provision for writing to it. I imagine you could conditionally bypass the GSU with some clever circuit design, but I'm not an electronics guy so I don't know for sure how practical this would be.

The most programmer-safe method of implementing such a bypass would be to only open the 'updateable ROM' chip for writing when it would normally be open for S-CPU read access. But it's possible to disable the GSU-to-SNES interrupt normally issued when STOP is executed, and if this has been done, finding out whether the GSU is still running requires a read of $3030 to obtain the value of the Go flag. It might be necessary to restrict write-enable to passively detectable safe states rather than all safe states, unless the core's run status is available on one of the pins... I guess snooping for $3030 reads counts as passive detection, and wouldn't be any weirder than snooping writes to $303A to detect the S-CPU taking control of the ROM bus...

Or you could simply allow writes whenever, and rely on the programmer to not do anything stupid...

I do wonder if it's possible for writes to U-ROM to feed back into the GSU and invalidate the contents of the ROM buffer. This might have to be guarded against, if the ROM buffer's behaviour in cases of RON=0 isn't safe.

Nikku4211 wrote: Fri Apr 15, 2022 6:33 pmThese are some cool what ifs, I can't wait until someone who has an SMW2 or SNES Doom cartridge decides to take out the GSU-2 chip and make a test cart with it to flash and test on.
There are some experts here who can make Super FX devcarts. I imagine that the pin 21 theory could be tested in the course of making such a thing.

As for the U-ROM idea, that one could be a bit more complex to implement, but I think an electronics expert should be able to figure out pretty quickly if it's possible.
calima
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Re: stretching the Super FX

Post by calima »

SRAM prices have not scaled like DRAM. Consider that CPU caches are SRAM usually, and only very recently at the high end are they getting big L3s (128mb or larger) (and that's slower SRAM than L1/L2).

Quick google gives 150$ for one 2mb SRAM. That's of course covid/ukraine pricing, but even in normal times it's going to be too expensive for a SNES cart.
93143
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Re: stretching the Super FX

Post by 93143 »

I'm seeing a low-power 45 ns 16 Mbit SRAM from Cypress Semiconductor for about $15 on Mouser. There also appears to be a low-power 55 ns 32 Mbit SRAM from Alliance Memory for about $25. These prices are admittedly on the low end, and the 32 Mbit stuff can get as high as ~$130 per chip.

Hidden-refresh 70 ns PSRAM appears to be on the order of a few bucks per chip at these sizes. I'm not picky, unless there's a catch I'm missing...
calima
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Re: stretching the Super FX

Post by calima »

PSRAM is cheap yeah, I can't comment on if it'd work for this use.
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Re: stretching the Super FX

Post by Pokun »

Is it supposed to be 2 MByte or 2 Mbit? I can't even find SRAM of the former size while the latter is cheap.
93143
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Re: stretching the Super FX

Post by 93143 »

https://www.mouser.com/c/semiconductors ... =16%20Mbit

I'd never heard of the website before, but this is one of the first things I found. Chip capacities are usually quoted in Mbits rather than MBytes; could that be the problem?
calima wrote: Sat Apr 16, 2022 12:19 amCPU caches
I had noticed the slow scaling of L2 caches at least.

In 1996 our family bought a PC with 24 MB of RAM, a 1.6 GB hard drive, and a 166 MHz Pentium, which had a 512 KB L2 cache. In 2002 we bought a new PC with 512 MB of RAM, an 80 GB (IIRC) hard drive and a 2 GHz Pentium 4, which had... 512 KB of L2 cache. In 2004 I bought myself a PC with 2 GB of RAM, a 160 GB hard drive and a 3 GHz hyperthreading Pentium 4, which had 1 MB of L2 cache.

In 8 years, CPU speed went up by a factor of 18 (with IPC and thread handling improving at the same time), RAM size increased by a factor of 85, hard drive capacity went up by a factor of 100, and L2 cache size went up by a factor of 2.
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Re: stretching the Super FX

Post by Pokun »

I don't know I think it often turns up empty when I search. Can't find through-hole options either.
creaothceann
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Re: stretching the Super FX

Post by creaothceann »

93143 wrote: Sat Apr 16, 2022 1:10 pm In 8 years, CPU speed went up by a factor of 18 (with IPC and thread handling improving at the same time), RAM size increased by a factor of 85, hard drive capacity went up by a factor of 100, and L2 cache size went up by a factor of 2.
I noticed that too...
In the 80s you could do your stuff in fast RAM (~32 KB) or you could swap out to slower memory (tape/disk).
In the 00s you could do your stuff in fast RAM (~32 KB) or you could swap out to slower memory (DRAM).

But that's just how the cost of high-speed memory is distributed against the cost of the other components in the computer, and the speed of these memory pools increased a lot.
My current setup:
Super Famicom ("2/1/3" SNS-CPU-GPM-02) → SCART → OSSC → StarTech USB3HDCAP → AmaRecTV 3.10
93143
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Re: stretching the Super FX

Post by 93143 »

Given that no one has mentioned it, can I infer that designing a circuit to safely bypass the GSU during writes to U-ROM is likely to be a tractable problem?

...

On the topic of the MSU1, does anyone have any idea what 4 GB of truly random-access zero-latency memory (e.g. mask ROM, NOR flash) would cost? I'm seeing $20 and up for just 2 Gbits of 110 ns NOR flash, and I have no idea whether the XtraROM in Switch games can be accessed randomly on SNES clock timescales.

In another thread, we toyed with the idea of a rough equivalent to the MSU1 using only period hardware. The tradeoffs were rather brutal, and the conclusion was that the best way to actually meet the MSU1 specification might be with a tape drive, since the spec doesn't mention seek time. Even a CD or MiniDisc would have far more latency than the high-speed SD cards used in the FXPak implementation, and those cards are still slow enough (up to 2 ms) that loading granular data from the MSU1 while also processing game logic requires a nontrivial solution like an IRQ-based loader that schedules itself based on when the Data Busy bit is expected to clear.

With NOR flash or mask ROM, Data Busy would clear faster than the CPU could read it, facilitating such stuff as (for example) high-granularity concatenation of visible open-world geometry data with appropriate LoD, or large numbers of onscreen actors and objects drawn from an extensive pool of richly animated normal-mapped pre-rotated sprites.

And with U-ROM instead of real ROM, processing streamed data would not need to involve so much expensive and conflict-prone RAM bus access. Nor would the low capacity of GPRAM restrict the number and size of streamed sprites, or require tight coordination between the GSU and the S-CPU to repeatedly switch them out while drawing a frame.

Unfortunately, writing the game to take advantage of zero-latency streaming memory could make it incompatible with the FXPak. I suppose this might qualify as an anti-piracy measure... It's probably possible to write the loader to degrade gracefully (particularly if it already needs to be IRQ-based to reliably dodge HDMA), but you might want to put up a warning at boot saying that the streaming memory is too slow and will affect performance.
lidnariq
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Re: stretching the Super FX

Post by lidnariq »

93143 wrote: Tue Apr 19, 2022 4:25 pm Given that no one has mentioned it, can I infer that designing a circuit to safely bypass the GSU during writes to U-ROM is likely to be a tractable problem?
It's likely. But I don't already know of anyone having stuck a logic analyzer on the GSU data bus.
93143 wrote: Tue Apr 19, 2022 4:25 pm On the topic of the MSU1, does anyone have any idea what 4 GB of truly random-access zero-latency memory (e.g. mask ROM, NOR flash) would cost? I'm seeing $20 and up for just 2 Gbits of 110 ns NOR flash
You literally cannot buy single NOR flash larger than 2gibit. (And that only in BGA)
and I have no idea whether the XtraROM in Switch games can be accessed randomly on SNES clock timescales.
Extremely unlikely. NDS already is a NAND-like protocol.
93143
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Re: stretching the Super FX

Post by 93143 »

So there's no way to get 4 GB of instantly readable memory for less than a few hundred dollars? Does anybody make mask ROMs big enough to assemble into an MSU1 data source, and what would the setup cost look like?

I suppose one could use NOR flash in an MSU1 passthrough device, and load it from a DVD that comes with the game, to avoid paying for the fast memory more than once. But that gets us back to the modern paradigm where it can take literally hours between putting in the disc and actually being able to play the game, and you never have enough storage for all your games to stay installed... Then there's the fact that such a device would have the same problem as the 32X, only worse: there isn't exactly a thriving market for games that would need it. In fact, the only one I can think of is my 3D open-world idea, and it's unlikely to ever see the light of day.

I'm feeling kinda cheated by modern technology, honestly. This doesn't sound a heck of a lot different from the '90s, where the only way to get CD-level storage capacity for consumer prices was to use a CD (or, y'know, a tape). Sure, there's tons you can do if you don't need the latency characteristics of a SNES cartridge, but if you do it looks like you're out of luck.

The SRAM situation is less serious, because it looks like there's hidden-refresh PSRAM that does the same job for a reasonable price. But that doesn't make it any less embarrassing that after 30 years of supposed geometric progress in integrated circuit technology, it's still too expensive to put a couple of megabytes of real SRAM on a SNES cartridge...
lidnariq
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Re: stretching the Super FX

Post by lidnariq »

93143 wrote: Tue Apr 19, 2022 8:16 pm So there's no way to get 4 GB of instantly readable memory for less than a few hundred dollars?
DRAM, probably. Not asynchronous, but latency should be low enough for this purpose.
Does anybody make mask ROMs big enough to assemble into an MSU1 data source, and what would the setup cost look like?
As far as I know, the per-unit costs on mask ROMs aren't enough better than the per-unit costs on Flash to be deemed acceptable to anyone other than maybe Nintendo. Plus modern huge NOR flash is already 2LC, so a SLC mask ROM will probably be more expensive per bit even after all is said and done.

NDS games are, theoretically, on large mask ROMs, if that part number starting with "23" can safely be used as an indication.
I suppose one could use NOR flash in an MSU1 passthrough device, and load it from a DVD that comes with the game, to avoid paying for the fast memory more than once.
Programming time for modern not-SST flash is slow. At least, compared to how big they are. Spansion/Cypress/Infineon S29GLxxT flash is worst case (and not atypically) 32 bytes in 512 microseconds, or almost a day to program 4GB.
after 30 years of supposed geometric progress in integrated circuit technology, it's still too expensive to put a couple megabytes of SRAM on a SNES cartridge...
SRAM was never cheap - you wanted lots of RAM, you went for DRAM. And without the volume market, no-one cared.
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