Demo Vision

Discuss hardware-related topics, such as development cartridges, CopyNES, PowerPak, EPROMs, or whatever.

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TmEE
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Re: Demo Vision

Post by TmEE »

There can be few photos with socketed chips out their sockets, it can help a little with few spots.
Fiskbit
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Re: Demo Vision

Post by Fiskbit »

Ben Boldt wrote: Tue May 31, 2022 2:55 pm U13 and U25 must be the RAMs that store the Gameboy video image. U38 is CIRAM. U45 is the normal Famicom latch that turns PPU AD0..7 into PPU A0..7. It is pinned out the same way as in the Famicom.
I think U13 and U25 are one Game Boy frame buffer and U16 and U28 are another. OUT1 should swap between them somehow.


I think we could really use a better image of the connections in the Game Boy. lidnariq annotated the one from Chris in this earlier post, but I find it difficult to follow some of the wires and see exactly where they hook up.
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Ben Boldt
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Re: Demo Vision

Post by Ben Boldt »

You are correct, those 4 RAMs are all working together. I was focused on U13 and U25 because they were closer to the PPU.

The data busses of the RAMs are multiplexed with the 8x 74HC541 between them, like so:
Video RAM Data Buss Multiplexing.jpg
I have not yet investigated the address busses of the RAMs, or the /CEs of the RAMs or '541s. Basically I found a handful of these connections visibly (maybe 30% of them), then was able to notice the patterns and extrapolate almost all of the unseen connections beneath the '541s. What a great tool from krzysiobal.

I also do not yet know where Input F and G come from, or where Output A goes.


Edit:
Also, something strange I noticed. These 2 74LS197 are different. I don't notice any manual-looking soldering. Why do you suppose they use 2 different vendors like that? (TI, ST) Is there some subtle difference in these chips?
197.jpg
seijurou
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Re: Demo Vision

Post by seijurou »

Hooo man I wish live ner by you and give you the machines to study the whole board.
If any pic or video is needed just let me know please.
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Ben Boldt
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Re: Demo Vision

Post by Ben Boldt »

seijurou wrote: Wed Jun 01, 2022 9:19 am Hooo man I wish live ner by you and give you the machines to study the whole board.
If any pic or video is needed just let me know please.
:D Thanks. I am OK for now with the photos that you already provided.

I found that the "Output A" in my diagram is connected directly to PPU AD0..7. In other words, Output A is feeding data into PPU D0..D7.

The 2 RAMs on the left (U13,U25) share a common address buss. The 2 RAMs on the right (U16, U28) also share a separate common address buss. These 2 address busses are driven by the 8x 74HC157s around the perimeter (quad 2-input multiplexer).

U19: A0,1,2,3 -> right RAMs
U12: A0,1,2,3 -> left RAMs

U5: A4,5,6,7 -> left RAMs
U10: A4,5,6,7 -> right RAMs

U6: A8,9,?,? -> left RAMs (unknown output pins are probably A10, A11)
U1: Maybe like U6 for right RAMs.

U9: A12,/CE2,/WE -> left RAMs (1 multiplexer not used, inputs terminated to GND.)
U4: Probably like U9 for right RAMs. (U4 has the same unused/terminated multiplexer as U9.)

I do not yet know the inputs to these multiplexers. I am guessing that the 74LS197 binary counters are counting up the address.
Fiskbit
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Re: Demo Vision

Post by Fiskbit »

seijurou wrote: Wed Jun 01, 2022 9:19 am Hooo man I wish live ner by you and give you the machines to study the whole board.
If any pic or video is needed just let me know please.
I'd really appreciate a picture of the inside of the Game Boy that shows more clearly how the cable connects. We have the image below, but it is difficult to follow the wires in this picture, and difficult to see exactly where they connect.

Image
Fiskbit
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Re: Demo Vision

Post by Fiskbit »

Ben Boldt: One thing I'm interested in is how the screen data is split between within a single RAM pair. Does each RAM have 1 bitplane, or does each RAM have complete tiles ($00-7F for one and $80-FF for the other)? I would expect that if the current buffer is switched mid-frame, the former would result in the last written tile sliver always having both bitplanes from the new image, while the latter could result in it having half a bitplane.
seijurou
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Re: Demo Vision

Post by seijurou »

Fiskbit wrote: Wed Jun 01, 2022 5:37 pm
seijurou wrote: Wed Jun 01, 2022 9:19 am Hooo man I wish live ner by you and give you the machines to study the whole board.
If any pic or video is needed just let me know please.
I'd really appreciate a picture of the inside of the Game Boy that shows more clearly how the cable connects. We have the image below, but it is difficult to follow the wires in this picture, and difficult to see exactly where they connect.

Image
Hello all.

I find a problem to do the pics.

When I was opening the gameboy the first 4 scrws was easy, fo the oter 2 I need open the battery door, but with the wire was in the middle.
well i found the way to open it, and see it was wit a kind a glue to avoid open it.
and where the other 2 screws is placed, is 2 big portions of the same grey glue avobe it and I can´t take it out.

Really sorry, but i can make any damege at the gameboys trying to do that.
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Ben Boldt
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Re: Demo Vision

Post by Ben Boldt »

I am making some progress each day mapping the main board. Once I get it better, it may be possible to figure out the protocol of the ribbon cable. When I feel like I have done most that I can do, I will share it.

I had 1 "bad" wire driving me crazy. KrzysioPCB counts wires that don't connect on both ends as "bad". You click the word BAD and it highlights them blue but I could not see it. So, I duplicated the entire project, then edited the photos to be pure white, thinking any blue line would show up clearly. Still, impossible to find it. I then exported the image with "bad" selected, opened in GIMP and viewed only the red color channel (i.e. make all the good/red wires invisible). THEN I found the tiny blue wire piece that was under a good wire in the center of a thru-hole. The blue anti-aliasing crust showed from beneath the red wire. WOW, very happy to solve the issue.

Do we know what the part# is of the PAL chip? I am wondering if some pins are known to be inputs or outputs, or special pins, etc. This may help to figure out some connections.
Fiskbit
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Re: Demo Vision

Post by Fiskbit »

seijurou wrote: Thu Jun 02, 2022 1:44 pm Really sorry, but i can make any damege at the gameboys trying to do that.
No problem, I totally understand. I've got some rare Famicom stuff I can't open without causing damage, which I'd like to avoid.
Ben Boldt wrote: Thu Jun 02, 2022 3:25 pm Do we know what the part# is of the PAL chip? I am wondering if some pins are known to be inputs or outputs, or special pins, etc. This may help to figure out some connections.
According to the parts list I duplicated in this post, it's an AMPAL20L10.
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Ben Boldt
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Re: Demo Vision

Post by Ben Boldt »

Fiskbit wrote: Thu Jun 02, 2022 4:52 pm
Ben Boldt wrote: Thu Jun 02, 2022 3:25 pm Do we know what the part# is of the PAL chip? I am wondering if some pins are known to be inputs or outputs, or special pins, etc. This may help to figure out some connections.
According to the parts list I duplicated in this post, it's an AMPAL20L10.
Ooo that's really helpful! Pins 1-11 and 13 have to be inputs, 14 and 23 have to be outputs, and pins 15-22 are bidirectional. This can help narrow things down.
AMPAL20L10.PNG
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Ben Boldt
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Re: Demo Vision

Post by Ben Boldt »

Concerning the 8 multiplexers (U1,U4,U5,U6,U9,U10,U12,U19) that switch the address bus going to the 4 video RAMs (U13,U16,U25,U28). The multiplexers are selecting between the "CHR" address bus and "something else". Ignoring the "something else" for now, it hooks up like this:

VRAM A0 <- PPU A0
VRAM A1 <- PPU A1
VRAM A2 <- PPU A2
VRAM A3 <- PPU A4 (yes: skipped PPU A3)
VRAM A4 <- PPU A5
VRAM A5 <- PPU A6
VRAM A6 <- PPU A7
VRAM A7 <- PPU A8
VRAM A8 <- PPU A9
VRAM A9 <- CHR A10 (CHR address bus supplied by MMC5)
VRAM A10 <- CHR A11
VRAM A11 <- CHR A12
VRAM A12 <- CHR A13

Does this make any sense that it skips PPU A3 like that? Traces can do strange things underneath chips but I am quite sure (~90%) that it does skip PPU A3.
Fiskbit
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Re: Demo Vision

Post by Fiskbit »

I believe skipping PPU A3 means that a single RAM holds just one of the bitplanes for all the tiles, rather than having all the bitplanes for half the tiles.

I'm curious how frame the data is written into the RAMs because I'd like to know what exactly should happen if the current buffer is switched in the middle of a Game Boy frame instead of during Game Boy vblank as it should be. If the RAMs can be written simultaneously, then a tile sliver will always be either from the new or old frame, but if they're written sequentially, then a tile sliver can have one new bitplane and one old one.
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Ben Boldt
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Re: Demo Vision

Post by Ben Boldt »

I mostly figured out the 2 74HC164 shift registers (U2, U3). Each has its own serial stream coming from P2, having been buffered by U49. On my diagram from earlier, the 8-bit parallel output of U2 connects as input F. U3 parallel output as input G. I have managed to untangle the traces in order:

QA --> D0
QB --> D1
QC --> D2
QD --> D3
QE --> D4
QF --> D5
QG --> D6
QH --> D7

/CLR is tied high on the shift registers. So these shift registers must be just blindly rolling through and logic elsewhere triggers it to write to Video RAM at the correct position, each 8 shifts. I am not yet sure what runs the clock input, it is hard to tell yet. Both shift register clock inputs are tied together and are driven by something on the far-left side of the board.
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Ben Boldt
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Re: Demo Vision

Post by Ben Boldt »

I have it pretty far along untangling the traces. Definitely there are going to be some issues. I think there are at least a few visible traces that are not yet traced, because I couldn't figure where the other end could go... Especially there are a bunch of unconnected vias and pins that probably do connect. The 74HC541s' /OEs don't all make great sense yet. But pretty close.

If anyone would like to take a stab at it, please do! Please let me know any things that you find out. Especially, if you just have theories how it works that would lend itself to predicting traces that we can't see, that would be really helpful too.

Demovision Dropbox download link (11.4 MB):
https://www.dropbox.com/s/ezxv1273yps1i ... on.7z?dl=0


KrzysioPCB Program / Instructions:
https://www.elektroda.pl/rtvforum/topic3247421.html

KrzysioPCB Program / Instructions (English Translation):
https://www-elektroda-pl.translate.goog ... _tr_pto=sc
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