Jitter (APU) what is it?

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Anes
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Jitter (APU) what is it?

Post by Anes »

I have been googling about electronics gitters and the only thing i know is that is has something to do with sync.

Well when i run Blargg's, the ones that test the apu timing it is always for me "odd jitter not handled properly".
I would like some explanation so i can correct that APU timming error.
THXS
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Quietust
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Re: Jitter (APU) what is it?

Post by Quietust »

I'm fairly certain the "jitter" refers to clock alignment - inside the 2A03, the CPU's clock is subdivided into two half-speed clocks, one "even" and one "odd", and those two clocks are used to drive the DMA controller as well as most of the audio logic.
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Re: Jitter (APU) what is it?

Post by Dwedit »

Blargg's test isn't checking for "jitter" in the audio signal sense.
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Re: Jitter (APU) what is it?

Post by Drag »

According to the wiki,
The APU frame counter is clocked every other CPU clock cycle. Writing to $4017 will reset the frame counter, but there's a delay of either 3 or 4 CPU cycles before it actually happens. If the write occurs on the same clock cycle the sequencer is clocked, the delay is 3 CPU cycles. If the write occurs in between sequencer clocks, the delay is 4 CPU cycles.

The fact that the delay is sometimes 3 and sometimes 4 CPU cycles is what I think the "jitter" is referring to, but I'm not 100% sure.
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Re: Jitter (APU) what is it?

Post by Fiskbit »

The difference in APU clock versus the CPU clock causes 'jitter' in most CPU/APU interactions. It's very relevant for DMA, but you even see it with the CPU's joypad OUT pins, which only update every APU cycle. The CPU/APU alignment is random at power-on, too, so it's another source of inconsistent behavior.
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Re: Jitter (APU) what is it?

Post by Drag »

Fiskbit wrote: Fri May 06, 2022 12:07 pmbut you even see it with the CPU's joypad OUT pins, which only update every APU cycle.
This is news to me, when was this discovered?
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Re: Jitter (APU) what is it?

Post by Fiskbit »

It was discovered I think last year by Perkka. It's a huge issue for the compatibility mode of his EPSM, which uses toggles on OUT1 to tell the expansion device when to read the data lines. Getting around this requires synchronization, which can be done with OAM DMA or silent DMC samples, but if you're using DMC, OAM DMA can't guarantee a correct alignment because DMC DMA near the end of OAM DMA takes an odd number of cycles. I've come up with a very gross workaround where the opcode after the write is a 'dummy' instruction that has the same value in the data bits as the value written, so the data is the same on both possible cycles, but I still need to put together a library that makes this work.

You can also detect your alignment by doing a one-cycle strobe with INC, where the strobe will be ignored depending on where it falls relative to the APU cycle.
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Re: Jitter (APU) what is it?

Post by Anes »

Drag wrote: Fri May 06, 2022 11:40 am According to the wiki,
The APU frame counter is clocked every other CPU clock cycle. Writing to $4017 will reset the frame counter, but there's a delay of either 3 or 4 CPU cycles before it actually happens. If the write occurs on the same clock cycle the sequencer is clocked, the delay is 3 CPU cycles. If the write occurs in between sequencer clocks, the delay is 4 CPU cycles.

The fact that the delay is sometimes 3 and sometimes 4 CPU cycles is what I think the "jitter" is referring to, but I'm not 100% sure.
I have an english missunderstading problem:
What does it mean every OTHER cpu cycle?
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Dwedit
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Re: Jitter (APU) what is it?

Post by Dwedit »

"Every Other" means half of them. You skip one, you process one, and so on.
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Re: Jitter (APU) what is it?

Post by Drag »

Yep, if it's "every" clock cycle: clock - clock - clock - clock.
If it's "every other" clock cycle: clock - skip - clock - skip.
If it's "every third" clock cycle: clock - skip - skip - clock - skip - skip.
...and so on, "every fourth", "every fifth", etc.
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