Identifying Address Buses A&B
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- jeffythedragonslayer
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Identifying Address Buses A&B
So I learned the snes has two address buses named A and B:
https://wiki.superfamicom.org/memory-mapping
Could someone please help me identify them on a schematic or board photo?
https://wiki.superfamicom.org/memory-mapping
Could someone please help me identify them on a schematic or board photo?
Re: Identifying Address Buses A&B
The 'A bus' is the 24-bit CPU address bus, which the CPU uses to access WRAM, cartridge RAM and ROM, and CPU (as in 5A22 S-CPU) registers. The 'B bus' is the 8-bit peripheral address bus, used for accessing APU, PPU, WRAM, and cartridge registers. They share a single data bus, which allows DMA (one bus is read while the other bus is written, so the data is passed directly between them without the CPU needing to pass the data along). The CPU address lines are typically named An (n= 0..23) or CAn, while the peripheral ones are PAm (m = 0..7). The size of the bus should be enough for you to tell which it is, though an older schematic I was recently looking at didn't even name the B/peripheral bus and instead referred to it and its read and write signals as D8-D17, for some reason.
- jeffythedragonslayer
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Re: Identifying Address Buses A&B
Thanks, so anything starting with CA here is part of bus A, and anything starting with PA is part of bus B:
https://wiki.superfamicom.org/cpu-pinout
https://wiki.superfamicom.org/cpu-pinout
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Re: Identifying Address Buses A&B
Just look at the schematic, the buses are clearly marked: https://wiki.superfamicom.org/schematic ... ematic-491
My current setup:
Super Famicom ("2/1/3" SNS-CPU-GPM-02) → SCART → OSSC → StarTech USB3HDCAP → AmaRecTV 3.10
Super Famicom ("2/1/3" SNS-CPU-GPM-02) → SCART → OSSC → StarTech USB3HDCAP → AmaRecTV 3.10
- jeffythedragonslayer
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- Joined: Thu Dec 09, 2021 12:29 pm
- jeffythedragonslayer
- Posts: 344
- Joined: Thu Dec 09, 2021 12:29 pm
Re: Identifying Address Buses A&B
On page 3-3-2 (3.2 APU I/O PORTS) of the official documentation I found this:
I presume this is talking about bus A. So A and B are the scene names for buses?
Ports 0-3 are ports which carry out data transmission to the SCPU through the SNES bus
Last edited by jeffythedragonslayer on Tue May 30, 2023 7:14 pm, edited 1 time in total.
Re: Identifying Address Buses A&B
Ports 0-3 are specific addresses on the B bus dedicated for communication between the S-CPU and S-SMP.
As far as we can tell, the "most correct" names for the two address buses are the labels on the WRAM, "C"PU and "P"eripheral. But no-one uses that anywhere.
As far as we can tell, the "most correct" names for the two address buses are the labels on the WRAM, "C"PU and "P"eripheral. But no-one uses that anywhere.
- jeffythedragonslayer
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Re: Identifying Address Buses A&B
Oh, of course it's the opposite of what I'd expect.
- rainwarrior
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Re: Identifying Address Buses A&B
A and B bus are referred to throughout the DMA section of the official docs. (See: 2-17-1.)
I don't think they ever get officially referred to by these names outside of the context of the DMA device, so maybe extending their meaning to a wider context is a "scene" thing?
- jeffythedragonslayer
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Re: Identifying Address Buses A&B
I found the DSP1 system block diagram (Figure 3-1-1) on 3-1-2 shows the A Bus and B Bus.rainwarrior wrote: ↑Thu Jun 30, 2022 8:46 pm I don't think they ever get officially referred to by these names outside of the context of the DMA device, so maybe extending their meaning to a wider context is a "scene" thing?