Talking about the DMA unit constraints of the 65816 of the snes...
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- Señor Ventura
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Talking about the DMA unit constraints of the 65816 of the snes...
Supposedly, due to the synchronous nature of its hardware the DMA must work at 3,58mhz, but due to the 2,68mhz +120ns of the WRAM, it works at a divisor x8, in the same way that an 200ns slow rom cause it.
The question is... What it we put a WRAM at 3,58mhz and under 80ns of time access?, Could the DMA work at 3,58mhz, then?
The question is... What it we put a WRAM at 3,58mhz and under 80ns of time access?, Could the DMA work at 3,58mhz, then?
- jeffythedragonslayer
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Re: Talking about the DMA unit constraints of the 65816 of the snes...
What does "divisor x8" mean?
- TmEE
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Re: Talking about the DMA unit constraints of the 65816 of the snes...
DMA runs at SNES master clock divided by 8. NTSC machines have it at (3579545 * 6) / 8
- Señor Ventura
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Re: Talking about the DMA unit constraints of the 65816 of the snes...
The question is, Do the DMA runs at masterclock divided by 8?, or is it adaptaed to its pipeline like that due to the constraints of the WRAM.
The cpu itself works with a divisor by 6 when reads from a fast rom, but the DMA is another thing... i remember having read about something is wrong with the adress bus lag to put the whole 24 bits out, and the slowness of the wram to sync the data in time (200ns?), so, due to that, the DMA runs divided by 8... so, 2,68mhz.
The thing is, Could a WRAM at 3,58mhz and less than 100ns do configure the DMA to run with a divisor by 6, letting reach a bus of 3,58mhz, and higher data transfers?.
Is the own DMA wich works at 2,68mhz by its own configuration itself?, or is the result of adapting itself to the smaller part of the pipeline.
The master clock works at 21,47mhz, and every component of the hardware has to work at a frequency divided by a multiple due to the high latency of the memory in the 90's.
The PPU's needs to work at 21,47 to draw the picture of a frame, so, you need run with a divisor by 2 to compensate the lag of many operations, and the latency of the memory... and, the slower the system is, the more you need higher dividers for time to sync correctly.
Last edited by Señor Ventura on Sat Jun 04, 2022 4:07 pm, edited 1 time in total.
- rainwarrior
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Re: Talking about the DMA unit constraints of the 65816 of the snes...
FastROM access is /6. SlowROM and WRAM access is /8.
So it's a 21 MHz master clock. Sometimes these divisions are called ~2.7 and ~3.6 MHz but both are an approximation since the CPU chooses the division on a per-cycle basis depending on which memory region (if any) is accessed. (See: Timing)
- rainwarrior
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Re: Talking about the DMA unit constraints of the 65816 of the snes...
The DMA is made to go at the lowest common denominator, so it's just always at 8, it doesn't matter where the A-bus is pointed. There isn't a way to configure it to go faster.Señor Ventura wrote: ↑Sat Jun 04, 2022 3:58 pmThe question is, Do the DMA runs at masterclock divided by 8?, or is it adaptaed to its pipeline like that due to the constraints of the WRAM.
Oddly the DMA registers can be both read and write at 6, which some people have suggested can be used as a tiny amount of fast RAM storage.
- Señor Ventura
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Re: Talking about the DMA unit constraints of the 65816 of the snes...
Not configuring, but changing the WRAM chip to another with 3,58mhz and 80ns of latency.rainwarrior wrote: ↑Sat Jun 04, 2022 4:41 pmThe DMA is made to go at the lowest common denominator, so it's just always at 8, it doesn't matter where the A-bus is pointed. There isn't a way to configure it to go faster.Señor Ventura wrote: ↑Sat Jun 04, 2022 3:58 pmThe question is, Do the DMA runs at masterclock divided by 8?, or is it adaptaed to its pipeline like that due to the constraints of the WRAM.
Oddly the DMA registers can be both read and write at 6, which some people have suggested can be used as a tiny amount of fast RAM storage.
My asking is about to know if the DMA is already prepared to work at that speed if the WRAM matches that frequency.
Registers and data uses the same bus, so...
- TmEE
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Re: Talking about the DMA unit constraints of the 65816 of the snes...
You can have the fastest possible chips but the DMA state machine will still run the speed it always has been. New CPU with updated logic is also required in addition to faster memories.
- jeffythedragonslayer
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Re: Talking about the DMA unit constraints of the 65816 of the snes...
@TmEE @Señor Ventura @rainwarrior I see thanks.
I suppose by "state machine" you are referring to the state of the DMA registers $420B, $420C, and $43n0 thru $43nF (n=0..7) and the rules for how those registers change.
- TmEE
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Re: Talking about the DMA unit constraints of the 65816 of the snes...
"State machine" is a composition of logic functions that go through a bunch of states(steps), using input from those registers, to perform a function, in this case bus cycles and related things that form DMA transfers.
https://en.wikipedia.org/wiki/Finite-state_machine
https://en.wikipedia.org/wiki/Finite-state_machine
- Señor Ventura
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Re: Talking about the DMA unit constraints of the 65816 of the snes...
So, do is the DMA irself wich runs at 2,68mhz, no matter what, even if the WRAM runs at 3,58mhz and a very low latency. Understood.
Registers at 3,58mhz when writes in some directions of the WRAM, and data at 2,68mhz in every case, then.
- jeffythedragonslayer
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Re: Talking about the DMA unit constraints of the 65816 of the snes...
Yes I'm familiar with FSMs I was just curious how much state is in the DMA state machine - similar to the registers that keep track of the source, destination, and progress of block moves.TmEE wrote: ↑Sun Jun 05, 2022 5:51 am "State machine" is a composition of logic functions that go through a bunch of states(steps), using input from those registers, to perform a function, in this case bus cycles and related things that form DMA transfers.
https://en.wikipedia.org/wiki/Finite-state_machine
- TmEE
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Re: Talking about the DMA unit constraints of the 65816 of the snes...
I don't think it is a whole lot in addition to the DMA registers, there aren't gonna be many states in the individual bus cycles. Someone who will be able to read the silicon shots that exist can uncover the exact details.