Instruction cycle comparison tool
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- NovaSquirrel
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Instruction cycle comparison tool
I made a little web tool to make the cycle information in the 65c816 datasheet interactive. It lets you quickly see cycle count, master cycle count (so you can see that, for example, lda (pointer) is slower than lda absolute,x despite having the same cycle count for 16-bit X/Y), available addressing modes, and what happens on each cycle.
https://novasquirrel.github.io/SnesInst ... CycleTool/
https://novasquirrel.github.io/SnesInst ... CycleTool/
- jeffythedragonslayer
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Re: Instruction cycle comparison tool
Good job on this. This will be very useful when I start writing compiler optimization passes. I was going to suggest renaming that leftmost column to "Addressing mode" because there are only three 65x instruction groups, but I see there are things in there like "branch taken" that are not an addressing mode.
- rainwarrior
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Re: Instruction cycle comparison tool
Thanks! This will definitely make it less tedious next time I need to count SNES cycles.
Re: Instruction cycle comparison tool
Some JS errors in older browsers:
https://novasquirrel.github.io/SnesInst ... escycle.js 136:0 SyntaxError: Unexpected identifier 'a16'
https://novasquirrel.github.io/SnesInst ... CycleTool/ 7:10 ReferenceError: Can't find variable: initTable
- jeffythedragonslayer
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Re: Instruction cycle comparison tool
So from playing with this tool, it sounds like the answer that Grog was too lazy to figure out is actually a formula that takes the checkboxes as boolean inputs:
https://wiki.superfamicom.org/grog's-gu ... n-the-snes
https://wiki.superfamicom.org/grog's-gu ... n-the-snes
- rainwarrior
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Re: Instruction cycle comparison tool
Are MVN/MVP missing?
-
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Re: Instruction cycle comparison tool
Maybe NovaSquirrel skipped it by accident; they're both on one page.
---
My notes:
1.) STP, WAI and WDM are not included, though cycle timings aren't that important for the first two, and the latter simply wasn't included in the datasheet's bus activity listings.
2.) It would be nice if the "16-bit accumulator" and "16-bit index registers" checkboxes automatically uncheck the "Emulation mode" checkbox, and vice versa.
3.) BRK, COP and RTI should change their timing depending on P.e, since in native mode the program bank byte is also pushed/pulled.
4.) Then there's this issue:
viewtopic.php?t=19163
"2-cycle opcodes with idle cycle will become bus read when an IRQ is to be triggered immediately after opcode completion. Affects the following opcodes:"
08 Accumulator: ASL DEC INC LSR ROL ROR
19a Implied: CLC CLD CLI CLV DEX DEY INX INY NOP SEC SED SEI TAX TAY TCD TCS TDC TSC TSX TXA TXS TXY TYA TYX XCE
http://forum.6502.org/viewtopic.php?f=4 ... t=0#p45508
"if an interrupt is asserted during the fetch of a one-byte, two-cycle instruction (CLC, SEC, TXY, etc.), the cycle of that instruction that is normally an I/O cycle also apparently turns into a read from the PC, at least for wait state purposes"
"[TXY] pretends to read an operand of the TXY instruction (although the instruction really has no operand), then on the first of the two dead bus cycles at the beginning of the interrupt sequence, without incrementing the address, it pretends to read another op code before showing a dead bus cycle for that second cycle."
---
My notes:
1.) STP, WAI and WDM are not included, though cycle timings aren't that important for the first two, and the latter simply wasn't included in the datasheet's bus activity listings.
2.) It would be nice if the "16-bit accumulator" and "16-bit index registers" checkboxes automatically uncheck the "Emulation mode" checkbox, and vice versa.
3.) BRK, COP and RTI should change their timing depending on P.e, since in native mode the program bank byte is also pushed/pulled.
4.) Then there's this issue:
viewtopic.php?t=19163
"2-cycle opcodes with idle cycle will become bus read when an IRQ is to be triggered immediately after opcode completion. Affects the following opcodes:"
08 Accumulator: ASL DEC INC LSR ROL ROR
19a Implied: CLC CLD CLI CLV DEX DEY INX INY NOP SEC SED SEI TAX TAY TCD TCS TDC TSC TSX TXA TXS TXY TYA TYX XCE
Code: Select all
// | x0 | x1 | x2 | x3 | x4 | x5 | x6 | x7 | x8 | x9 | xA | xB | xC | xD | xE | xF |
// ---+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
// 0x | | | | | | | | | | | 0A | | | | | |
// 1x | | | | | | | | | 18 | | 1A | 1B | | | | |
// 2x | | | | | | | | | | | 2A | | | | | |
// 3x | | | | | | | | | 38 | | 3A | 3B | | | | |
// 4x | | | | | | | | | | | 4A | | | | | |
// 5x | | | | | | | | | 58 | | | 5B | | | | |
// 6x | | | | | | | | | | | 6A | | | | | |
// 7x | | | | | | | | | 78 | | | 7B | | | | |
// 8x | | | | | | | | | 88 | | 8A | | | | | |
// 9x | | | | | | | | | 98 | | 9A | 9B | | | | |
// Ax | | | | | | | | | A8 | | AA | | | | | |
// Bx | | | | | | | | | B8 | | BA | BB | | | | |
// Cx | | | | | | | | | C8 | | CA | | | | | |
// Dx | | | | | | | | | D8 | | | | | | | |
// Ex | | | | | | | | | E8 | | EA | | | | | |
// Fx | | | | | | | | | F8 | | | FB | | | | |
"if an interrupt is asserted during the fetch of a one-byte, two-cycle instruction (CLC, SEC, TXY, etc.), the cycle of that instruction that is normally an I/O cycle also apparently turns into a read from the PC, at least for wait state purposes"
"[TXY] pretends to read an operand of the TXY instruction (although the instruction really has no operand), then on the first of the two dead bus cycles at the beginning of the interrupt sequence, without incrementing the address, it pretends to read another op code before showing a dead bus cycle for that second cycle."
My current setup:
Super Famicom ("2/1/3" SNS-CPU-GPM-02) → SCART → OSSC → StarTech USB3HDCAP → AmaRecTV 3.10
Super Famicom ("2/1/3" SNS-CPU-GPM-02) → SCART → OSSC → StarTech USB3HDCAP → AmaRecTV 3.10
- NovaSquirrel
- Posts: 483
- Joined: Fri Feb 27, 2009 2:35 pm
- Location: Fort Wayne, Indiana
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Re: Instruction cycle comparison tool
I initially misread MVN/MVP on the datasheet as having different timing on the last iteration, and I wasn't sure how to include that, but after double checking I can see that it was just the datasheet author emphasizing what the next instruction read would be. I went and fixed all of that I think?
-
- Posts: 611
- Joined: Mon Jan 23, 2006 7:47 am
- Location: Germany
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Re: Instruction cycle comparison tool
Yep, seems to be fixed.
(Do you want to include XSlow memory regions? It probably only affects programs that don't enable automatic controller polling and read the input controller registers 4016/7 directly; afaik there's no other hardware mapped to that region.)
(Do you want to include XSlow memory regions? It probably only affects programs that don't enable automatic controller polling and read the input controller registers 4016/7 directly; afaik there's no other hardware mapped to that region.)
My current setup:
Super Famicom ("2/1/3" SNS-CPU-GPM-02) → SCART → OSSC → StarTech USB3HDCAP → AmaRecTV 3.10
Super Famicom ("2/1/3" SNS-CPU-GPM-02) → SCART → OSSC → StarTech USB3HDCAP → AmaRecTV 3.10
Re: Instruction cycle comparison tool
How exactly is this supposed to be read? I get the gist of it, but why would having fewer master clock cycles per cycle make an operation go slower?
Re: Instruction cycle comparison tool
It ... doesn't? What makes you think that?
Re: Instruction cycle comparison tool
Well, setting it to / 8 gives smaller numbers in the total cycle column than setting it to / 6 (because it's dividing the master clock count by a larger number).
Re: Instruction cycle comparison tool
How much time would it take, relative to pretending that all instructions always took exactly 6 (running at 3.6MHz) or 8 (2.7MHz) clocks.
In other words, the "Total column" is the number of "master clocks", or is the number of master clocks divided by 8, or the number of master clocks divided by 6.
In other words, the "Total column" is the number of "master clocks", or is the number of master clocks divided by 8, or the number of master clocks divided by 6.
Re: Instruction cycle comparison tool
Can we sticky this thread?