A few questions about how the S-SMP and S-DSP communicate on the hardware level

Discussion of hardware and software development for Super NES and Super Famicom. See the SNESdev wiki for more information.

Moderator: Moderators

Forum rules
  • For making cartridges of your Super NES games, see Reproduction.
Post Reply
Jessdoesstuffidk
Posts: 1
Joined: Sun Oct 30, 2022 12:30 am

A few questions about how the S-SMP and S-DSP communicate on the hardware level

Post by Jessdoesstuffidk »

Hi, this is my first post here, sorry if this isn't allowed.


So I've been reading up on how the S-DSP functions for a project I'm working on, and I have a few questions that I’ve so far not been able to find information about online. In no particular order they are:


Does the divide-by-12 counter used to form CPUK start with a known value when reset, or does it just start off with a random number? Presumably a simple binary counter is used to divide down the 24.576MHz from the crystal oscillator, so is that loaded with a set value when reset/power is applied, or just random? For example, if one were to supply two S-DSPs with the same 24.576MHz signal into their XTALIs, would their PD3 lines be in phase? Is this already documented somewhere and I missed it, or is this more something that one would just have to test with an oscilloscope and see?


Is the PD3 line active-high or active-low? All I can really find is “CPUK Clock-Enable used to create effective SMP frequency of 1.024MHz (to S-SMP)”, which doesn’t say if the S-SMP clock cycle happens when the PD3 line is high or low (diagram of what I mean below). This would be fairly easy to test in a working SNES, but I don’t have one so I’d have to borrow/buy one which isn’t ideal.

Active high PD3:
/‾\_____/‾\_____/‾\_____/‾\_____/‾\_____ effective clock
/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_ CPUK
/‾‾‾\___/‾‾‾\___/‾‾‾\___/‾‾‾\___/‾‾‾\___ PD3


Active low PD3:
____/‾\_____/‾\_____/‾\_____/‾\_____/‾\_ effective clock
/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_ CPUK
/‾‾‾\___/‾‾‾\___/‾‾‾\___/‾‾‾\___/‾‾‾\___ PD3



Is the PD2 line R/#W, or #R/W? From the same document it says “MD Bus tri -state control signal used when S -SMP is accessing SRAM (from S-SMP)”, which as with the one for PD3, while it’s very useful for knowing the purpose of the pin, it’s missing very important information. Presumably when the SMP isn’t accessing the RAM the pin is in the high-impedance state, but it’s not entirely clear what happens with it when it is. I’d be inclined to believe that most likely when reading the line is pulled high and when writing low, as is the case with the 6502, but it’s not really clear. It’d be possible to test but would be somewhat more difficult.

Thanks in advance for the help!
Post Reply