NESRGB v4 22.31 Clock Buffer Circuit

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Fluxy
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Joined: Mon Jan 23, 2023 2:17 am

NESRGB v4 22.31 Clock Buffer Circuit

Post by Fluxy »

Image

Hi everyone,
So I decided to Mod my NTSC front loading NES with Tim's NESRGB kit. v4-22.31. I got a problem(s) and I'm 90% positive I pinpointed the issue. A sync issue. Quoting from Tim's website.

Clock hardware bug.
Description: Version 4 hardware is more susceptible to noise on the clock signal than version 1/2/3 hardware. Previous versions had a clock input with schmitt trigger hysteresis of 400mV. Version 4's clock input also has a schmitt trigger on the clock input, but the hysteresis is only 200mV.
Symptom: Noise on the clock line can cause the NESRGB board to become unsynchronised with the PPU. This looks like colour fringes on the edge of objects and the picture moving left/right by one pixel.
Hardware affected: Normal NESRGB installations should be unaffected. The Bakutendo mod for installing NESRGB boards into original Famicom consoles is very likely to be affected.
Solution: Insert a clock buffer circuit between the NES clock signal and the NESRGB board.

https://etim.net.au/nesrgb/background_fault/nesrgb40/

It's odd because this statement says a NTSC front loading NES shouldn't be affected however the description is spot on. Only difference is my moded NES works for about 5 or 10 minutes before these problem starts up. Console works for 5 or 10 minutes then red light goes off and power is off. I turn off power button and turn on power again then the issues start.

I'm on here to see if anyone else has had this issue and or has built this buffer circuit. I'm also on here seeking good tips on how to do this. I'm just beginning to dive into this. Learning as I go. This project is going to take me a good minute and I'll update as I progress.

Any feedback would be helpful. Thanks.
TheiMac74
Posts: 1
Joined: Wed May 24, 2023 11:04 am

Re: NESRGB v4 22.31 Clock Buffer Circuit

Post by TheiMac74 »

Did you find any more information about this? I have a NTSC top loader that occasionally displays this issue with the color fringing.Image
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aquasnake
Posts: 515
Joined: Fri Sep 13, 2019 11:22 pm

Re: NESRGB v4 22.31 Clock Buffer Circuit

Post by aquasnake »

try this:
TEST.png
pixel_clk is determined by this sys_clk by frequency division, this clock is a sensitive signal, while the excessively long adapter line of the rgb-nes board will introduce interference.

Placing the buffer circuit as close as possible to the pin18 of the ppu may achieve effective improvement, and increasing the value of absorption resistor will reduce signal reflection
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