I have this MMC5 dev cart I use for NES prototyping; it sure beats using the Famicom Disk System.
The big switch on it is to select between the CL/SL modes.
The MMC5 is a fun time. If the extended attribute name table mode can be combined with the split screen mode, then making a game like Panel de Pon for NES becomes a lot easier. I have to try this out...
When writing to the RAM @ $5C00-5FFF inside the MMC5, when the Internal extended RAM mode ($5104) is configured for 00 or 01 (name table modes):
"(2)Writes are only allowed when the PPU is rendering, otherwise a $00 is written"
So, does this mean that the CPU data will be written to the RAM on the next PPU read cycle from the pattern tables (which implies there is a temporary storage register)? It is really interesting that you can write to the RAM from the CPU port while it's also being used by the PPU for reading, because that can make some things easier
MMC5 dev cart + split screen mode.
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