Famicom AV (HVC-101) - weird broken delayed audio issue; schematic + comparision

[krzysiobal]

I recently was asked to fix malfunctioning Famicom AV (HVC-101). Audio was missing or sometimes it worked but with few seconds delay after power-up. Looking at the audio section revals someone was trying to do some nasty job here.
Signs of rust and corrosion nearby might also contribuded to this.
//audio-mess.jpg


I was trying to track the audio path but I couldnt do it easily, also I couldnt find any schematics so I think it was a good opportunity to restore the schematic and do some comparision against regular famicom.

//top-tracks.jpg
//top_corr2.jpg
//bottom_corr1.jpg
//sch.png


Top layer, similarly like in regular famicom, is covered by some weird layer that covers almost all traces. There is just tiny clearence around pads so If you look at it under light, you can see at least if a trace is coming out of a pad and from which direction.

I don't know what is purpose of that and why it is only on the top layer. Probably it's an opaque soldermask, because there are no third and four layer (everything fits perfectly in 2 layers). This makes reverse engineer proces 10 times slower though luckily not impossible. There are a dozen of smd-spots on the bottom layer so I marked them as test-pads in the schematics.

//top-layer.jpg


Differences against regular Famicom:
* Single BU3266S chip is used that replaces 74HC368+74HC368+74LS139.

* CPU-/ROMSEL, PPU/CE, CPU-RAM/CE and PPU-/A13 are generated by it.
On regular FC it takes around 20ns delay between M2 rise and /ROMSEL fall, on AV-FC it is around 10ns
On regular FC high level for /ROMSEL is around 4V, on AV FC it is 5V, so if cartridge contains 74HC chips, they might not work properly on regular FC
//m2_to_romsel_av_fc.png
//m2_to_romsel_reg_fc.png


This chip has built-in pull-ups for 4016.D0/D1/4017.D0/D1/D2/D3/D4 so no external 10k pullups like in Famicom are needed.
* 4016.D2 (microphone input in reg FC) is tied to VCC
* 4016.CLK and 4017.CLK are directly tied to CPU 4016_BUF_/OE and 4017_BUF_/OE (with pull-ups for unknown reason), not to buffered and inverted M2 like in regular FC. So when DMC fetch occurs during 4016/4017 read, it will produce just one clock edge.
//bu3266.png



* Clock signal is common to CPU and PPU and it is generated with just single transistor:
//clock.png


* Video amp circuit uses 300R+100R resistor, not 2.2k+220R and there is just one stage PNP amp (not PNP+NPN like in most famiclones):
//video_amp.png


* Audio is amplified by one of the inverting gates of the BU3266S (with 68k feedback resistor, not like 100k in FC). This amplified audio is fed into pin 45 of carttridge and pin 46 is then driving this additional single-transistor amp, whose output is finally fed into AV connector
//aud_amp.png


* EXP port contains the same pins like EXP in regular FC, tough pins 5/6 (D4/D3) of the 7-pins joypad connectors are not connected to anythin (that would explain why many people solder two additional wires to add zapper support for P2 port.

* Big cap on the DC line is wired before the power switch, so if the console is turned on, cap is still energised and some parasite resistance will still srive fractions of milliamps
//power.png


Audio issue in the AV famicom
After power up, it takes few seconds for the audio to appear. I made a special rom that after start, does nothing but drives OUT0 low, then immediatelly high and plays one note infinitely so you can measure how much it takes for audio to appear after CPU starts executing its very first opcode.
CH1 = OUT0
CH2 = audio taken from input of BU3266
CH3 = audio taken from the output of BU3266
You can see it, the sound level need 6 seconds to go high.
//audio_issue1.png


So my guess is that the inverter gate of BU3266 is broken and the sound output in fact is not amplified at all, but it sinks from the input to the output through this 68k feedback resistor, thats why the delay appears.

Since the digital inverter is used as analog amplifier, it's hard to tell if that's the case. By looking at some instant in time, when input is feed by about 2.5V, output is also around 2.5V
//audio_issue2.png


I cut off both the input and output audio traces from the BU chip, connected PPU-A13 to its INV1-IN line ans checked INV1-OUT line and it was properly inverted, so no idea what is the reason. But then I soldered single transistor amp in the circuit (ommiting BU chip) and sound started to appear from the very first second after power up, so looks like BU chip was culprit indeed.
//transistor-amp.jpg

[lidnariq]

I noticed that the inverter-as-amplifier that's part of the MMC5 seems to be really slow by digital standards (mostly in terms of a low slew rate despite being unloaded). Perhaps the three inverters-or-amplifiers in the BU3266/70 might be different from each other?

[krzysiobal]

I've just noticed you suggested on wiki that pins 30/31 were intended for CIC clock based on topology. I'm wondering they were rather designed to be part of CPU/PPU clock generator (01/02 - connects 21MHz crystal, 30 - CPU clock, 21 - PPU clock)

[lidnariq]

That's a very good hypothesis too - is the OSC3 system fast enough to support that? The oscilloscope capture from your previous thread implies a delay around 15ns for one inverter...