Mapper 670

[tepples]

A couple nights ago, I took a couple hours to sketch out a design for a mapper using a 74HC670 and a few combinational chips. Features include three switchable 8 KiB banks and one switchable 4 KiB bank, allowing use of DPCM. It can be put together with four chips (plus PRG ROM, CHR RAM, and lockout defeat) for a 128 KiB PRG capacity or six chips (plus PRG ROM, CHR RAM, and lockout defeat) for a 2 MiB PRG capacity.

Memory map

$4018-$7FFF: Handled by other logic
$8000-$9FFF: Switchable bank 0
$A000-$BFFF: Switchable bank 1
$C000-$DFFF: Switchable bank 2
$E000-$EFFF: Switchable bank 3
$F000-$FFFF: Fixed bank

Register interface

Registers at $8000, $A000, $C000: Bank select

Code: Select all

7654 3210
     ||||
     ++++- Select 8 KB bank

Register at $E000: Bank select

Code: Select all

7654 3210
     ||||
     ++++- Select 8 KB bank whose first half is mapped

Parts summary

PRG ROM (128 KiB)
CHR RAM (8 KiB)
Lockout defeater
74HC670: register file
74HC08 Quad 2-input AND: Compute MapperWrite and FixedF000
74HC32 Quad 2-input OR: Apply FixedF000
74HC02 Quad 2-input NAND: Compute PRG ROM /OE
Optional:
Additional 670 and 32 to allow PRG up to 2 MiB

Combinational logic signals

MapperWrite = R/W AND CPU /A15
Determines when the CPU is writing to the mapper.

FixedF000 = (A14 AND A13) AND A12
Determines when the CPU is trying to access the fixed 4 KB bank.

PRG ROM A16-A13 = Q3-Q0 OR FixedF000

PRG ROM /OE is computed as in ANROM.

Use of 670

74HC670 is a 4-entry 4-bit register file. It has the following pins:
Power VCC, GND
Write address WB-WA
Write data D3-D0
Write enable /WE
Read address RB-RA
Read value Q3-Q0
Read enable /RE

In this mapper they are assigned thus:
D3-D0 = CPU D3-D0
RB-RA, WB-WA = CPU A14-A13
/RE = 1
Q3-Q0 to PRG ROM A16-A13
/WE = MapperWrite


So is this viable?

[kyuusaku]

Why is a fixed bank necessary? I don't see why a few bytes of reset code couldn't be placed in all banks to free ORs.

Also, what about mirroring? A 2 bit MUX can be built with a single 7400, then all you'd need is a register bit. With 3 more NAND-2s you could get SRAM decoding: !(Phi2 && nCE && A14 && A13) = nWRAMCE

[Memblers]

I've been looking at the 74HC670 also for a while. It's out of production. Digikey has some in small quantities, in SSO-16 packaging though. If they run out there's might not be any more, short of buying thousands at a time.. Nice looking chip, I want to use it but I'm still kinda leery about designing it into something.

Nice mapper too. 128kB is way too small though. I don't see much utility in having a fixed 4kB page though (besides having the vectors in a known place on power-up, which isn't needed really). If I was gonna have a couple 4kB pages, I'd rather have those on the CHR-RAM.

Don't forget mirroring control. Hard-wired 2-screen isn't very fun for development (unless this is to be a game cart). And WRAM address decoding. I've been thinking about using a PAL to reduce the chip count. But PALs and register files are a bit expensive (not much, but as far as standard logic chips go).

[kyuusaku]

HC isn't necessary, (DIP) LS670s are very available from Jameco at only $1.

[tepples]

I've been looking at the 74HC670 also for a while. It's out of production.

The 74HC170 or 74LS170 is similar, albeit with open collector outputs instead of 3-state.

Nice mapper too. 128kB is way too small though.

Adding another 170/670 and another 32 allows another 4 bits of address, for PRG ROM up to 2 MiB. Take that MMC3!

I don't see much utility in having a fixed 4kB page though (besides having the vectors in a known place on power-up, which isn't needed really).

In addition to reset-related tasks, the fixed bank could handle other common tasks, such as a jump table to allow subroutines in different banks to call each other.

Don't forget mirroring control. Hard-wired 2-screen isn't very fun for development (unless this is to be a game cart).

I try to keep replication in mind when imagining mappers.

[Memblers]

HC isn't necessary, (DIP) LS670s are very available from Jameco at only $1.

Right on, I'd forgotten about searching for the LS parts because they're usually more expensive and less available, but not in this case. They're not listed in my Jameco catalog either (I see them now on the site though).

[Bananmos]

Nice-looking design. I haven't seen the 670 chip before. It seems taylor-made for memory mapping.

If I'm not mistaken, 32kB SRAM chips aren't more expensive than 8kB ones these days. So having a 32kB CHR-RAM and adding another 670 for 2kB CHR-RAM switching would be a nice option. (possibly battery-backed if your game needs non-volatile RAM but won't need quick access to it)

I'd recommend making one fat development board that contains everything wished for (1MB ROM, 32kB CPU-RAM, 32kB CHR-RAM with 2kB switching, batteries for both the CPU-RAM and CHR-RAM chips, mirroring control, and maybe even 1 kB switching of nametables if you use the 32kB CHR-RAM for nametables as well)

For a production, you could then choose which of the possible features you actually need and populate the board accordingly. You could then easily hard-wire the things that are overkill, or even manufacture a specific subset-board for your creation if you intend to sell lots of carts. That's a far better alternative than trying to compromise everything from the very start.

[Memblers]

I've been looking at the 74HC670 also for a while. It's out of production.

The 74HC170 or 74LS170 is similar, albeit with open collector outputs instead of 3-state.

That's good to know, that chip seems to be even less common (and LS version only), but it's out there at least. If I make a board with it I'll leave room for pull-up resistors in case that chip ever comes around.

It's hard to beat having 4*4bit registers in a 16-pin chip.

[Memblers]

Thanks for the inspiration, tepples.

Here's what I've got so far with my (newest, heheh) experimental mapper design. If I'm lucky and it fits effectively, it'll only be a 2-chip mapper.

74LS670

WA0 = A0
WA1 = A1
RA0 = A14
RA1 = WRAM /CE
Q0..3 = shared with PRG-ROM and RAM upper address lines
/WR = decoded bankswitch write enable
/RD = +5V

Registers will be at $48xx (or possibly $58xx). This is because the Squeedo MCU will be at $50xx. Besides Squeedo, 4 mapper regs. 2 for PRG banks, one for WRAM banks, and an extra one I'm not sure what to do with.

The catch is that you've got 16kB-sized pages (out of 512kB of ROM), but the $8000-$BFFF bank can only access even numbered pages, and vice-versa for the other bank. Not a problem, I think (one normally assembles with pre-set code origin anyways, right?).

CHR banks will still be controlled by the Squeedo MCU.

The only way I'll do this, is if I can fit the address decoding + mirroring control in a little PLD (which is basically a super-small CPLD, for the uninitiated). That's what I'm going to start researching now. That way I'll have one less chip, and a better mapper than the original Squeedo for a relatively nominal cost increase.

[Zepper]

How do you design the main cartridge board?

[tepples]

The catch is that you've got 16kB-sized pages (out of 512kB of ROM), but the $8000-$BFFF bank can only access even numbered pages, and vice-versa for the other bank. Not a problem, I think (one normally assembles with pre-set code origin anyways, right?).

What if you end up with 24 even banks and 8 odd banks? Or what if you want to have code, data, and audio in view at once?

[Memblers]

The catch is that you've got 16kB-sized pages (out of 512kB of ROM), but the $8000-$BFFF bank can only access even numbered pages, and vice-versa for the other bank. Not a problem, I think (one normally assembles with pre-set code origin anyways, right?).

What if you end up with 24 even banks and 8 odd banks? Or what if you want to have code, data, and audio in view at once?

I thought of that after I posted. Seems like a small enough trade-off, with sound code for example you could have an alternate copy in the other bank which would only put you down like a 3kB with NT2. Beats my usual standard of 32kB paging, where the 3kB hit would be for every needed bank.

If anyone has more than 256kB of some data to put in a non-code bank, please raise your hand and maybe show a demo.

[Memblers]

I believe I've made it fit in a PAL. I haven't simulated the logic yet, though (nor do I have a PAL programmer). Only downside I can see is if I build a version without the Squeedo PIC, you won't be able to swap CHR banks or change the mirroring mode.