nesdev.org

What is the maximum safe access delay for using EPROMs in carts?

If my math is correct, one NES clock cycle is about 560 ns. I'm not sure when the bus needs data after it asserts a chips CS line, but it seems like ~500 ns access time would be the slowest, or perhaps 500/2 for 250 ns. That's still pretty slow for EPROMs, right?

Well, for PRGROM about anything will do (to be exact you have to mesure the high time of M2, and that is the exact maximum acess time allowed), and you'd need to be more carefull with CHRROM, because the processor is 3 times slower (I guess 120ns or less EPROMs are okay, like SNES' Fastrom games). Again, the only real answer is to take an oscilloscope and measure the low time of CHR /RD.

If I remember right, for NTSC, the PRG /CS line is active for 6 master cycles (at 21.477272 MHz), or about 279 ns. The CHR /RD line (during screen rendering) is active for four master cycles, or about 186 ns. PAL timing is slower, so if it works for NTSC it'll also work for PAL.