CopyNES and Other Matters

kevtris · Post by **kevtris** » Sun Jul 08, 2007 6:40 pm

As you know, I haven't been really doing much NES related for awhile. I kinda moved on to other things for the time being since I essentially finished my NES on a chip and fully debugged the hardware. It's at 100% compatibility except for two things- FDS drive (sound works) and VRC7 sound (mapper works).

The CopyNES supplies are almost exhausted. I have maybe 20 PCBs left and a smattering of parts, and maybe 10 or 15 cables. I have not made any more kits since it is a pain in the ass. Been thinking about offering up complete boards ready to go for a bit more than the cost of the kits, you just desolder your NES CPU, drop my board in, plug in the CPU.

The benefit of this is I can personally test each board after construction to make sure it works.

On the matter of CIClones, they are in production and you just have to email or pm me with your needs. Bunnyboy has been using them with great success (I think

in his carts. After a few initial speedbumps, I have a good method for production and testing of them.

No Carrier · Post by **No Carrier** » Sun Jul 08, 2007 7:05 pm

Glad to hear that CIClones will be available. I am hoping to get a few and some of BB's blank boards!

NC

Jagasian · Post by **Jagasian** » Sun Jul 08, 2007 10:29 pm

Is your NOAC the FPGA NES or did you redesign a NOAC from scratch in hopes of seeing ASICs made? Have you had a chance to check out the NES PowerPak?

kevtris · Post by **kevtris** » Mon Jul 09, 2007 12:28 am

Jagasian wrote:Is your NOAC the FPGA NES or did you redesign a NOAC from scratch in hopes of seeing ASICs made? Have you had a chance to check out the NES PowerPak?

Yes, it's my FPGA. I have been working on a smattering of other chips in my FPGA besides just the NES...

I recreated the OPL3 (aka YMF262) in my FPGA and I have it playing some FM synth tunes. It's a simple matter to drop the code for that into my NES core to get VRC7 audio.

I was going to redesign it to use a Cyclone 3 when the higher density versions of the chip are available. I am going for "SNES level" and "genesis level" emulation capabilities on the next spin of the board.

Also, I really have a chubby to make a real time zooming mandelbrot generator on the FPGA

Using all of the multipliers, it appears to be possible to do the billion or so multiplies a second it takes to get at least 30fps fractal panning/zooming. As far as I know, this kind of thing is still very difficult to perform on a PC even today.

Lately I haven't been doing a whole heck of alot of programming/design work, since I have been dorking around on Second Life making and selling products.

dvdmth · Post by **dvdmth** » Mon Jul 09, 2007 4:18 pm

How is NES 2.0 coming along?

kevtris · Post by **kevtris** » Mon Jul 09, 2007 6:51 pm

dvdmth wrote:How is NES 2.0 coming along?

NES2.0 is 100% implemented in my FPGA NES and works great. I just haven't had time to release more than the formal specs, unfortunately.. I did make up a list of all the changes I made to the ROMs I had to make everything work.

Guess I could post that if people have some interest

dvdmth · Post by **dvdmth** » Tue Jul 10, 2007 7:54 am

kevtris wrote:NES2.0 is 100% implemented in my FPGA NES and works great. I just haven't had time to release more than the formal specs, unfortunately.. I did make up a list of all the changes I made to the ROMs I had to make everything work.

Guess I could post that if people have some interest

Please do. I know bunnyboy would love to have NES 2.0 support in his PowerPak, and implementing it will be much easier if we knew how the ROMs are configured for it (particularly the sub-mapper field).

An NES 2.0 upgrade utility would also be nice, particularly one that performs a database lookup and sets the fields automatically (although a manual editor can also come in handy).

gannon · Post by **gannon** » Tue Jul 10, 2007 8:29 am

NES 2.0 spec is still here. Yes, an upgrade utility would be nice. I built a header cleaner/upgrader based on Nestopia's database, but that only had ~200 entries

dvdmth · Post by **dvdmth** » Tue Jul 10, 2007 10:36 am

gannon wrote:NES 2.0 spec is still here. Yes, an upgrade utility would be nice. I built a header cleaner/upgrader based on Nestopia's database, but that only had ~200 entries

Umm... Nestopia's database has around 5000 entries.

gannon · Post by **gannon** » Tue Jul 10, 2007 11:45 am

Whoops, you're right, ~5075, must've been reading the wrong line of my debug output

Edit: On closer look, I must be handling the database wrong, getting a lot of duplicate CRCs

dvdmth · Post by **dvdmth** » Tue Jul 10, 2007 12:54 pm

Are you taking into account the four bytes at the beginning of the file that contain the number of entries present? Are you making sure to read the file in little-endian byte order? (I'm using a PowerPC Mac, so I often have to deal with byte ordering issues since the PowerPC is big-endian and x86 is little-endian.)

If you're reading the file correctly, the CRC's should be in ascending order.

gannon · Post by **gannon** » Tue Jul 10, 2007 1:11 pm

dvdmth wrote:Are you taking into account the four bytes at the beginning of the file that contain the number of entries present?

Missed that when I looked through the original code to find out the db format. Database all working now, need to code a little bit for inserting the data into the NES 2.0 header format, but that's easy

Josh · Post by **Josh** » Tue Jul 10, 2007 10:27 pm

I recreated the OPL3 (aka YMF262) in my FPGA and I have it playing some FM synth tunes. It's a simple matter to drop the code for that into my NES core to get VRC7 audio.

Any possibility that you could write a document on how the VRC7 actually works on a hardware level? Yamaha's documentation on its FM chips really sucks, and there doesn't seem to be any third-party documentation that isn't simply a rewriting of the YM application manuals. The manuals say stuff like what bits control envelope speed, but don't say things like how many actual clock cycles this corresponds to, or how many entries there are in the sine wave table, or a million other things you really need to know to emulate the chip accurately.

Jeroen · Post by **Jeroen** » Wed Jul 11, 2007 2:08 pm

I was wondering about your fpga nes. Can it be modified to run cartridges? Also is it possible it wil sometime become avaible as an asic? (I know a few people that could use more accurate noacs *coughcoughbenheck.comcough*
and pay for it to)

Post by **tepples** » Wed Jul 11, 2007 4:33 pm

Jeroen wrote:I was wondering about your fpga nes. Can it be modified to run cartridges?

I seem to remember reading that the whole reason that the whole NES plus mappers is on a single FPGA is to keep from having to use 72 level shifters to translate between 5.0 V and 3.3 V logic.