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When you do a bankswitch (like on an UNROM) is there any delay associated with it?
I'm 99.9% sure that the only cost is the actual CPU instruction costs (LDA , STA etc..) but I still wanted to check because I know some calls cost a lot more in CPU cycles than the actual instruction. (like STA 4014 to invoke Sprite DMA which costs at least 512 CPU cycles)
There is the delay in the form of logic gate propagation time, but the outputs in all commercial mapper stabilize long before even the next half-CPU cycle.