Sprite DMA & background questions

[Zepper]

- During a sprite DMA transfer (4014h), does the PPU run? Can IRQs/NMI be requested/triggered during this period?

- What cycle and line does the PPU render its first visible background pixel? And when does it plot into screen?

- Thanks.

[Disch]

- During a sprite DMA transfer (4014h), does the PPU run?

The PPU is unaffected. All $4014 does is copy bytes to $2004.

Can IRQs/NMI be requested/triggered during this period?

Yes and no.

Yes, NMIs and IRQs still happen as normal. But the CPU is effectively "stalled" until the DMA is complete. So any NMI/IRQ that occurs during DMA won't occur until an instruction after the DMA is complete. Example:

Code: Select all

STA $4014  ; if IRQ occurs during DMA
LDA $8000
; IRQ happens here

What cycle and line does the PPU render its first visible background pixel? And when does it plot into screen?

Cycle 0 of the first rendered scanline.

The NTSC frame:

Code: Select all

--------------------------
1 "idle" scanline
--------------------------

20 scanlines of Vblank

--------------------------
1 "prerender" scanline  (same as rendered scanlines, but no pixels output)
--------------------------


240 rendered scanlines


--------------------------

See this doc for details:

http://nesdev.com/2C02%20technical%20reference.TXT

[blargg]

Can IRQs/NMI be requested/triggered during this period?

Yes and no. Yes, NMIs and IRQs still happen as normal. But the CPU is effectively "stalled" until the DMA is complete. So any NMI/IRQ that occurs during DMA won't occur until an instruction after the DMA is complete. Example:

Code: Select all

STA $4014  ; if IRQ occurs during DMA
LDA $8000
; IRQ happens here

To be clearer than "any NMI/IRQ that occurs during DMA" (what does it mean for it to "occur"?): The 2A03 has an NMI input connected to a flip-flop. When the input is asserted, the flip-flop is set and isn't cleared until the NMI vector is jumped to. There is also an IRQ input without any flip-flop. Both sources are sampled on some clock of each instruction. If the NMI flip-flop is set or the IRQ input is asserted at that moment (and the I flag is clear), the NMI/IRQ vector will be jumped to after the instruction finishes. So, the question is, where is it sampled for the STA $4014 that initiates sprite DMA? Since the $4014 write is the last cycle of the instruction, it seems like they'd be sampled at the beginning of sprite DMA, so if an interrupt was requested anytime after that during those 512 or so DMA clocks, it wouldn't occur until after the next instruction. Only a test will tell for sure...

[Zepper]

-deleted-

[Dwedit]

The PPU would do whatever it would otherwise do if someone did 513 CPU cycles worth of writes to $2004.

[hap]

Code: Select all

STA $4014 ; if IRQ occurs during DMA 
STA $4014
; IRQ happens here?

*edit*, added 2 more

STA $4014 ; if IRQ occurs during DMA 
STA $4014 ; if NMI occurs during DMA 
; IRQ or NMI?

STA $2000 ; $80, NMI after next instruction
STA $4014
; NMI?

[blargg]

I tested on my NES. Left column is time of IRQ, relative to some arbitrary point. Right column is low byte of saved PC on stack when IRQ is handled. Comments below show the location of the IRQ for each low byte. For example, having the IRQ occur at +3 and +4 clocks puts it just before the LDA. Having it occur at +5 and +6 clocks puts it just after the LDA.

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  0: 0
  1: 1
  2: 1
  3: 2
  4: 2
  5: 4
  6: 4
  7: 7
  8: 7
  9: 7
 10: 7
 11: 8
...
526: 8
527: 9
528: 9
529: 10

; 0
nop
; 1
nop
; 2
lda #$07
; 4
sta SPRDMA
; 7
nop
; 8
nop
; 9
nop
; 10
nop