byuu wrote:Can anyone please post all of the known technical data on the chip so far? Eg all the other registers, memory mapping, etc? I'd like to start emulating the other features of this chip as soon as possible.
I strongly suggest figuring out how to use your copier to play with these cartridges. If need be you can always disable the CIC chip, load a program into ram with the copier, remove copier and insert cartridge. I can give you a memory explorer program which should let you then play with any cartridge.
DarkForce has a doc out on the net somewhere, but I couldn't find it. I have saved a post he put in a thread once
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When the cart powers up, banks $C0-$CF are mapped to the program rom and banks $D0-FF are mapped to the data rom. So like I said, if you can read properly from $D0, there is nothing stopping you from reading $E0 and $F0 as well.
See info below for how to map data rom banks.
DF
<SPC7110 Info, Reverse Engineered by Dark Force>
SPC7110 Rom Map
=====================
Far East of Eden Zero
40mb total: 8mb program rom (000000-0FFFFF) + 32mb data rom (100000-4FFFFF)
Super Momotarou Happy Train
24mb total: 8mb program rom (000000-0FFFFF) + 16mb data rom (100000-2FFFFF)
program rom mapped to $C0:0000-$CF:FFFF/$80:0000-$8F:FFFF always
data rom in 8mb chunks can be mapped to hirom areas using the bank mapping regs ($4831/2/3)
default mapping: first 24mb of data rom mapped to $D0:0000-$FF:FFFF
SPC7110 Decompression Ram Map
$50:0000 - $50:FFFF data decompressed from data rom by spc7110
when reading from bank $50, the offset address is ignored ($00:XXXX), instead bytes are
always read sequentially from the start of the bank ($50:0000) after each
new decompression. register $4800 is linked to the same read index as reading from bank $50
SPC7110 Sram Map
$00:6000 - $00:7FFF sram 8k
SPC7110 Mirroring
$xx:4800 - $xx:7FFF register and sram banks mirrored at $00 - $3F, $80 - $BF
defval: = default power-on/reset register value
SPC7110 Registers
$4800 DECOMPRESSED DATA CONTINUOUS READ PORT: returns a decompressed value from bank $50 and decrements 16 bit counter value at $4809/A by 1
$4801 COMPRESSED DATA TABLE POINTER: ($0000FF) low offset, defval:00
$4802 COMPRESSED DATA TABLE POINTER: ($00FF00) high offset, defval:00
$4803 COMPRESSED DATA TABLE POINTER: ($FF0000) bank, defval:00
$4804 COMPRESSED DATA TABLE INDEX: index of 32 bit compressed data pointer (big-endian), defval:00
$4805 DECOMPRESSED DATA OFFSET: ($00FF) low byte of offset in bank $50, defval:00
$4806 DECOMPRESSED DATA OFFSET: ($FF00) high byte of offset in bank $50, defval:00
$4807 DMA CHANNEL FOR DECOMPRESSION, set to match snes dma channel used for compressed data, defval:00
$4808 C r/w option, unknown, defval:00
$4809 COMPRESSION LENGTH COUNTER: ($00FF) low byte, defval:00
write: set start counter value low byte
read: get counter value low byte
auto-increment: after each sequential read from bank $50
$480A COMPRESSION LENGTH COUNTER: ($FF00) high byte, defval:00
write: set start counter value high byte
read: get counter value high byte
auto-increment: after each sequential read from bank $50
$480B DECOMPRESSION COMMAND MODE: see decompression command modes, defval:00
$480C DECOMPRESSION FINISHED STATUS: high bit set = done, high bit clear = processing, cleared after successful read,
high bit is cleared after writing to $4806, $4809/A is set to compressed data length, defval:00
$4810 DATA ROM CONTINUOUS READ PORT: returns a byte from data rom at data rom pointer location, defval:00
$4811 DATA ROM POINTER: ($0000FF) r/w low offset, defval:00
$4812 DATA ROM POINTER: ($00FF00) r/w high offset, defval:00
$4813 DATA ROM POINTER: ($FF0000) r/w bank offset, defval:00
bank offset is zero based from start of data rom: banks $00-$3f data rom -> $10-$4f full rom
$4814 DATA ROM POINTER ADJUST: ($00FF) low byte, defval:00
$4815 DATA ROM POINTER ADJUST: ($FF00) high byte, defval:00
$4816 DATA ROM POINTER INCREMENT: ($00FF) low byte, defval:00
$4817 DATA ROM POINTER INCREMENT: ($FF00) high byte, defval:00
$4818 DATA ROM COMMAND MODE: bit field control of data rom pointer (see data rom command mode byte), defval:00
write: set command mode,
read: performs action instead of returning value, unknown purpose,
command mode is loaded to $4818 but only set after writing to both $4814 and $4815 in any order
$481A DATA ROM READ AFTER ADJUST PORT: returns a byte from data rom at data rom pointer location + adjust value ($4814/5), defval:00
$4820 16 BIT MULTIPLICAND: ($00FF) low byte, defval:00
32 BIT DIVIDEND: ($000000FF) low byte of low word, defval:00
$4821 16 BIT MULTIPLICAND: ($FF00) high byte, defval:00
32 BIT DIVIDEND: ($0000FF00) high byte of low word, defval:00
$4822 32 BIT DIVIDEND: ($00FF0000) low byte of high word, defval:00
$4823 32 BIT DIVIDEND: ($FF000000) high byte of high word, defval:00
$4824 16 BIT MULTIPLIER: ($00FF) low byte, defval:00
$4825 16 BIT MULTIPLIER: ($FF00) high byte, defval:00
$4826 16 BIT DIVISOR: ($00FF), defval:00
$4827 16 BIT DIVISOR: ($FF00), defval:00
$4828 32 BIT PRODUCT: ($000000FF) low byte of low word, defval:00
32 BIT QUOTIENT:($000000FF) low byte of low word, defval:00
$4829 32 BIT PRODUCT: ($0000FF00) high byte of low word, defval:00
32 BIT QUOTIENT:($0000FF00) high byte of low word, defval:00
$482A 32 BIT PRODUCT: ($00FF0000) low byte of high word, defval:00
32 BIT QUOTIENT:($00FF0000) low byte of high word, defval:00
$482B 32 BIT PRODUCT: ($FF000000) high byte of high word, defval:00
32 BIT QUOTIENT:($FF000000) high byte of high word, defval:00
$482C 16 BIT REMAINDER: ($00FF) low byte, defval:00
$482D 16 BIT REMAINDER: ($FF00) high byte, defval:00
$482E MUL/DIV SIGN: bit 0: on = signed calculation, off = unsigned calculation, defval:00
$482F MUL/DIV FINISHED STATUS: bit 7: on = processing, off = finished,
high bit is set after a write to multiplier or divisor regs $4825/$4827, defval:00
$4830 SRAM CHIP ENABLE/DISABLE: bit 7: on = enable, off = disable, defval:00
$4831 ROM BANK MAPPING A $D0:0000-$DF:FFFF, see bank mapping modes, defval:00
$4832 ROM BANK MAPPING B $E0:0000-$EF:FFFF, see bank mapping modes, defval:01
$4833 ROM BANK MAPPING C $F0:0000-$FF:FFFF, see bank mapping modes, defval:02
$4834 HARDWARE DECOMPRESSION ENABLE: bit 0: unknown, bit 1: on = enable, off = disable, defval:00
$4840 RTC CHIP ENABLE/DISABLE: bit 0: on = enable, off = disable, defval:00
$4841 RTC INDEX/DATA PORT:
first write after rtc enable: rtc command mode byte (see rtc command modes)
subsequent writes: index of rtc register to read/write (00-0f)
read: returns value of indexed rtc register
auto-increment of register index occurs after each subsequent read/write
$4842 RTC READY STATUS: bit 7: on = ready, off = still processing, tested before reading rtc data
high bit cleared after successful read
Decompression Command Modes:
00 - manual decompression, $4800 is used to read directly and sequentially from the data rom
02 - hardware decompression, data gets decompressed mapped to $50:0000-$50:FFFF, $4800 can be used to read sequentially from the compressed data pointer address
Note: decompression mode is activated after writing to $4806 and finishes after reading the high bit of $480C
Data Rom Command Mode Byte:
X6543210
||||||||
|||||| \__ : 00 - use 1 as the offset increment value, add immediately after reading $4810
|||||| : 01 - use $4816 as offset increment, add immediately after reading $4810
|||||| : 10 - use $4814 as offset increment, see below for when to add
|||||| : 11 - unused
||||||____ : 0 - unsigned calculation for $4816
||||| 1 - signed calculation for $4816
|||||_____ : 0 - unsigned calculation for $4814
|||| 1 - signed calculation for $4814
||||______ : 0 - offset increment gets added to $4811/2/3
||| 1 - offset increment gets added to $4814/5
| \_______ : 00 - disable offset addition
| : 01 - 8 bit offset addition using $4814, immediately after writing to $4814/5
| : 10 - 16 bit offset addition using $4814/5, immediately after writing to $4814/5
| : 11 - 16 bit offset addition using $4814/5, only after reading $481A
|_________ : unused
Note: the data rom command mode is activated only after registers $4814 and $4815 have been written to, regardless of the order they were written to
Bank Mapping Modes Values for $4831/2/3:
00 - use data rom 000000-0FFFFF for mapping
01 - use data rom 100000-1FFFFF for mapping
02 - use data rom 200000-2FFFFF for mapping
03 - use data rom 300000-3FFFFF for mapping
Note: the data rom areas are mirrored according to rom size, i.e. the value 02 for a 24mb rom means use data rom 000000-0FFFFF
RTC Command Modes:
03 - normal sequential read/write mode
0c - sequential read/write mode 2
other commands unknown as of yet
RTC Registers (8 bit values): [default values]
00 - seconds 1's digit 00
01 - seconds 10's digit 00
02 - minutes 1's digit 00
03 - minutes 10's digit 00
04 - hours 1's digit 00
05 - hours 10's digit 00
06 - day of month 1's digit 01
07 - day of month 10's digit 00
08 - month 1's digit 01
09 - month 10's digit 00
0a - year 1's digit 00
0b - year 10's digit 00
0c - day of week 00
0d - control register 01
0e - control register 0F
0f - control register 06
RTC Control Register Bits:
Register 0d
XXXXXX10
||_ : 0 - normal timer operation
| 1 - pause rtc registers updating, time still increments normally
|__ : 0 - disable rtc interrupts
1 - enable rtc interrupts
Register 0e
XXXX3210
\\\|_ : unknown
Register 0f
XXXXX210
|||_ : 0 - normal
|| 1 - stops timer and resets seconds to 00 (date gets set to 01/01/00 00:00:00 ??)
||__ : 0 - normal timer operation
| 1 - stop timer
|___ : 0 - 12 hour time, bit 2 of "hours 10's digit" register contains am/pm bit (am=0,pm=1)
1 - 24 hour time
The comments on 480A/9 should say auto-
decrement not increment. (as even he hints in discussion of reg 4800)
Here's some more data (posted earlier in this thread) copied here for reference
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http://nesdev.com/bbs/viewtopic.php?p=34184#34184
Charles MacDonald:
About the FEoEZ memory map, I took my SNES memory map viewing program and adapted it to run on the Game Genie, so I could plug in the FEoEZ cart and examine it after my program relocated itself to work RAM. (and yeah, I added a wire to connect the missing clock signal that isn't passed through the Genie to the cart edge connector).
What I got was this:
Banks
00-1F : SRAM @ 6000-7FFF, U1 ROM @ 8000-FFFF (1MB)
20-3F : SRAM @ 6000-7FFF, U2 ROM @ 8000-FFFF (banked?)
40-4F : Unused (reads return last value on data bus; e.g. bank address)
50 : 64K SPC7110 internal RAM
51-57 : Unused (as above)
58 : SPC7110 data port
59-7D : Unused (as above)
80-9F : 8K SRAM @ 6000-7FFF, U1 ROM @ 8000-FFFF (1MB)
A0-BF : 8K SRAM @ 6000-7FFF, U2 ROM @ 8000-FFFF (banked?)
C0-CF : U1 ROM (1MB)
D0-DF : U2 ROM (banked)
E0-EF : U2 ROM (banked)
F0-FF : U2 ROM (banked)
The SRAM is the 8K RAM chip on the PCB. The internal RAM is, I assume, internal the SPC7110 because there is no other RAM on the board to account for it, and it makes sense the chip would have some place to store its results.
As discussed at length earlier in this thread. bank $50 is not ram. It is just reg $4800 (although 480b settings may affect whether it is active or not, I forget at the moment). I don't know what he means about bank $58.
If anyone has more info please post.
