nesdev.org

Fx3 wrote:

dreampeppers99 wrote:I'm writing a debugger to nes, then I need to know :

opcode:
cycles:
size:

of each instruction so I can disassembler properly.

I'm looking around and saw it http://members.chello.nl/taf.offenga/illopc31.txt. Need I to implemente all illegal opcodes? And if I don't implement it the final Size/Position of instructions will modify... invalidating my assembler?

You wouldn't go anywhere with this. You must know what each opcode does, instead of alpha-times of 6502 emulation, using cycle tables. Such table wouldn't bring accuracy, plus, how useful would be your disassembled log file?

Well I'm closer to this...

I want use it as I use my eclipse debugger.

tepples wrote:

Dwedit wrote:Games do use the illegal opcodes

Which is probably why Nintendo abandoned making the Super NES fully backward-compatible with the NES.

I think the reason is the fact that it would have been way too much effort in making the SNES PPU doing the same kind of fetches as the NES PPU does, to ensure mapper compatibility.

WedNESday wrote:There are some illegal opcodes that actually go as far as reading from a memory location like ADC Absolute, X ($7D), but without actually doing any kind of addition or whatever.

WHAT?! Really? damn.
Is this NES-specific or general to the 6502?
Why it doesn't say anything on most docs about it?

PS: sorry for waking up the dead (posts)

Many (all?) of the two- and three-byte NOPs do this.

blargg wrote:Many (all?) of the two- and three-byte NOPs do this.

Sorry, is this an answer to my post?

When I wrote the post I though WedNESday was saying that ADC Absolute, X ($7D) didn't do any kind of addition.

Now I'm suspecting that what he really meant was that an unofficial NOP read from memory, like ADC...

Now I'm suspecting that what he really meant was that an unofficial NOP read from memory, like ADC...

This is the case (whether or not that's what he meant)

The 2 and 3 bytes NOPs have addressing modes just like LDA/ADC and whatever. And the memory accesses are the same as they would be for any other read-only opcode with the same addressing mode.

The only difference is that a NOP is performed instead of ADC/LDA or whatever.

Ok got it. So an apparently innocent unofficial NOP could be triggering a read on a memory-mapped register.

Ok, anyway, for now I'll just let unofficial/undocumented/illegal opcodes fall to a default: case and trap them with a debug message.
When the cpu core is decently tested, if I find ROMs that run such opcodes, then I'll go on and implement them.

We really should call these unofficial "NOPs" something different, since they are clearly not NOPs; a (non-PC-related) memory read and being more than one byte long is not merely "no operation". Maybe FAD: fetch and discard.

If anything, the multibyte NOPs not using immediate addressing are analogous to the "preload" instruction on some modern pipelined CPUs, which is a non-blocking fetch and discard intended to prefill the cache. I'd assign mnemonic PLD.

I would imagine a lot of uses for an instruction like DCP compared to official DEC because DCP supports more advertising modes.

some docs call them SKB and SKW (SKip Byte/Word).

Which is my point, those lie. I was thinking of LDN (load no-op), though I don't think they modify the status flags. DLD (dummy load) or something. Then you'd have DLD $1234,y for example, making it clear there's a memory access (that takes an extra cycle on page-crossing).

DLN maybe? "Dummy Load No operation"

What I really want to know is, after you guys finish this arguably pointless discussion, how do you plan on making this new name official, considering that the presence of the 6502 is much wider than its use on the NES. We can't even change stuff that only pertains to the NES (iNES header, for example)!

I think NOP is just fine, since it is effectively a NOP.

The addressing mode implies the memory access, not the intsruction. For example, you expect LSR $xx to access memory, but don't expect LSR A to. Therefore you can't tell from 'LSR' alone whether or not memory will be accessed.

For NOPs which have non-implied addressing mode, the addressing mode indicates the memory access. No need to rename NOP.

A few references call the 2- and 3-byte NOPs "SKB" and "SKW" for skip byte and skip word.

If I wrote a guide on how to make the best use of unofficial opcodes, would I be crazy?