SNES PowerPak

Discussion of hardware and software development for Super NES and Super Famicom. See the SNESdev wiki for more information.

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bunnyboy
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SNES PowerPak

Post by bunnyboy »

So I had some old photos from March sitting around, and people happened to find them just a few days before it is all public :)

Basic specs is 128Mbit of SDRAM to handle (bigger than) the biggest games ever. Load games off a CF card, loading times in a few seconds. Optional DSP1 chip for Mario Kart. Works on NTSC, PAL, clones, Super Famicom, basically anything I have tested.

Available now at www.retrousb.com

Image
MatthewCallis
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Post by MatthewCallis »

Please tell me this will play the translate Star Ocean non S-DD1 hack.
bunnyboy
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Post by bunnyboy »

You mean the 96Mbit version? ~25 secs to load but boots fine. http://www.youtube.com/watch?v=Uy4SFfoT5LY
ailI
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Post by ailI »

128 Mbit of SDRAM... That's amazing! Did you have to use donors for the lockout and DSP1 chips? It must be expensive to keep supply of DSP1 donors, so I can definitely understand the extra charge.
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NESHomebrew
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Post by NESHomebrew »

See, See, I'm not insane!!

Can't wait to try this out.
peppers
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Post by peppers »

interesting, are any additional enhancement chips like the super fx chip for example planned and are they possible to implement?

Since there is no mention of it and the real DSP1 is installed manually I assume not, but I thought i would ask.

btw u thinkin about any N64 carts by chance?
I would like one and I would rather not buy from neoflash
Last edited by peppers on Wed Nov 04, 2009 6:51 pm, edited 4 times in total.
MatthewCallis
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Post by MatthewCallis »

bunnyboy wrote:You mean the 96Mbit version? ~25 secs to load but boots fine. http://www.youtube.com/watch?v=Uy4SFfoT5LY
The destruction of them will slow down greatly.
bunnyboy
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Post by bunnyboy »

Enhancement chips are simply not happening. DSP/C4 can probably be quickly done with a PIC, but by the time you make the Super FX you are a significant way to doing the entire system. For the small number of games and the big increase in hardware it was a design decision early on not to do them.
tepples
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Post by tepples »

bunnyboy wrote:You mean the 96Mbit version? ~25 secs to load but boots fine.
Especially when you compare it to the loading time of a PlayStation 1 game.
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Banshaku
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Post by Banshaku »

This is good news. What I like this time is that I don't need any adapter to use on a super famicom. This could be an interesting option for snes programming in a near future since this is what I would have the most interest in such a device. For now, I will concentrate on my nes project.

Is it a coincidence that it just came out before the Christmas season? :P
bunnyboy
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Post by bunnyboy »

Yes its coincidence, I was expecting to have them done much earlier than this. Chinese customs had a different idea...
shadowkn55
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Post by shadowkn55 »

Nice work. I guess my 96mbit repro board can wait a little longer. How big is the onboard sram? As far as the mappers as concerned, would I be able to write one that uses bankswitching so that I could take advantage of the full 128mbit if necessary?
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kyuusaku
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Post by kyuusaku »

bunnyboy wrote:Enhancement chips are simply not happening.
By you or anyone? XC2S30 again?
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Bregalad
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Post by Bregalad »

This is amazing I didn't exept it to come so early !! Too bad I have only a crappy 16MB CF cart that don't work with the NES power pak, can't wait until I find a better one.

I am curious what is the CIC inside it ? Not that i really care as I have a CIC re-rooter I always use to play non-PAL SNES games, but I guess it wasn't reverse-engineered, was it ?
Useless, lumbering half-wits don't scare us.
bunnyboy
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Post by bunnyboy »

shadowkn55 wrote:Nice work. I guess my 96mbit repro board can wait a little longer. How big is the onboard sram? As far as the mappers as concerned, would I be able to write one that uses bankswitching so that I could take advantage of the full 128mbit if necessary?
The SDRAM is 128Mbit, bankswitching should be possible to use the entire thing. There is no other SRAM chip on there.

Right now the mapper chops up the address range into 4Mbit sections which can be nothing/rom/ram. Block RAM is used for that so granularity could be much smaller. DSP and the 6000-7FFF SRAM are handled separately.
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