Mid frame vertical scroll

Jaffe · Post by **Jaffe** » Sat Dec 05, 2009 6:45 pm

After lots of reading and thinking, I think I understand PPU scrolling pretty well. However, there are some things that just seem strange. Why is it that the FV scroll counter is only set mid-frame if you write to the registers in the order $2006, $2005, $2005, $2006?

tokumaru · Post by **tokumaru** » Sat Dec 05, 2009 7:01 pm

Because the first write to $2006 always clears one of the bits related to the fine vertical scroll in the VRAM address (bit 14). By writing to the registers in this particular order, you handle this problematic write first, so that the fact that it clears a bit doesn't matter. The next write, to $2005, sets the vertical scroll, which will not be corrupted by the first $2006 write, because you've already done it.

This happens to be the best order for setting the scroll mid-frame because the first $2006 write will not corrupt the vertical scroll and because the second $2006 write will cause the temporary VRAM address to be copied to the actual register.

Jaffe · Post by **Jaffe** » Sat Dec 05, 2009 7:11 pm

Ah, thanks! Now everything makes sense. I thought it was some weird aspect of the PPU and that the scroll register table in the 2C02 Technical Reference document didn't apply to what happens mid-frame.