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Code: Select all

tests/sprdma_and_dmc_dma/sprdma_and_dmc_dma.nes FAILED
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7461977F
SPRDMA and DMC DMA

Failed

tests/sprdma_and_dmc_dma/sprdma_and_dmc_dma_512.nes FAILED
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2EA11D4D
SPRDMA and DMC DMA

Failed

Code: Select all

// $4010
void write_dmc_reg_0(uint8_t value) {
    static uint16_t const dmc_ntsc_periods[] =
      { 428, 380, 340, 320, 286, 254, 226, 214, 190, 160, 142, 128, 106, 84, 72, 54 };

    if (!(dmc_irq_enabled = value & 0x80)) {
        dmc_irq = false;
        update_irq_status();
    }
    dmc_loop_sample = value & 0x40;
    dmc_period      = dmc_ntsc_periods[value & 0x0F];
}

// $4011
void write_dmc_reg_1(uint8_t value) {
    unsigned const old_dmc_counter = dmc_counter;

    dmc_counter = value & 0x7F;

    if (dmc_counter != old_dmc_counter)
        channel_updated = true;
}

// $4012
void write_dmc_reg_2(uint8_t value) {
    dmc_sample_start_addr = 0x4000 | (value << 6);
}

// $4013
void write_dmc_reg_3(uint8_t value) {
    dmc_sample_len = (value << 4) + 1;
}

Code: Select all

void tick_apu() {
    ...
    if (--dmc_period_cnt == 0) {
        dmc_period_cnt = dmc_period;
        clock_dmc();
    }
    ...
}

static void clock_dmc() {
    if (dmc_bits_remaining > 0) {
        if (dmc_sample_buffer & 1) {
            if (dmc_counter < 126) {
                dmc_counter += 2;
                channel_updated = true;
            }
        }
        else
            if (dmc_counter > 1) {
                dmc_counter -= 2;
                channel_updated = true;
            }
        dmc_sample_buffer >>= 1;
        if (--dmc_bits_remaining == 0 && dmc_bytes_remaining > 0)
            load_dmc_sample_byte();
    }
}

Code: Select all

// $4015
uint8_t read_apu_status() {
    uint8_t const res =
      (dmc_irq                   << 7) |
      (frame_irq                 << 6) |
      (cpu_data_bus            & 0x20) | // Open bus
      ((dmc_bytes_remaining > 0) << 4) |
      ((noise_len_cnt       > 0) << 3) |
      ((tri_len_cnt         > 0) << 2) |
      ((pulse[1].len_cnt    > 0) << 1) |
       (pulse[0].len_cnt    > 0);
    frame_irq = false;
    update_irq_status();
    return res;
}

// $4015
void write_apu_status(uint8_t value) {
    ...

    // We need to clear the DMC IRQ before handling the DMC enable/disable in
    // case a one-byte sample is loaded below, which will immediately fire a
    // DMC IRQ
    dmc_irq = false;
    update_irq_status();

    // DMC enable bit. We model DMC enabled/disabled through the number of
    // sample bytes that remain (greater than zero => enabled).
    if (!(value & 0x10))
        dmc_bytes_remaining = 0;
    else {
        if (dmc_bytes_remaining == 0) {
            dmc_sample_cur_addr = dmc_sample_start_addr;
            dmc_bytes_remaining = dmc_sample_len;

            // If a sample byte is currently being played, the sample is
            // restarted only after it has finished
            if (dmc_bits_remaining == 0)
                load_dmc_sample_byte();
        }
    }

    ...
}

Code: Select all

static void load_dmc_sample_byte() {
    // Timing: http://forums.nesdev.com/viewtopic.php?p=62690#p62690
    // TODO: Open bus?
    assert(dmc_bytes_remaining > 0);
    assert(dmc_bits_remaining == 0);

    dmc_sample_buffer = prg(dmc_sample_cur_addr);

    // We use tick() since the PPU as as well as the rest of the APU should
    // keep ticking during the fetch.
    // TODO: Is this done before or after the IRQ is generated? (Should be
    // invisible though.)
    unsigned const delay = doing_oam_dma ? 2 : doing_read ? 4 : 3;
    for (unsigned i = 0; i < delay; ++i) tick();

    dmc_sample_cur_addr = (dmc_sample_cur_addr + 1) & 0x7FFF;

    // Putting this after the delay ensures that we can't get a recursive
    // invocation of load_dmc_sample_byte(), since it can only called be called
    // through dmc_bits_remaining going from 1 to 0 while the CPU is stalled
    dmc_bits_remaining = 8;

    if (--dmc_bytes_remaining == 0) {
        if (dmc_loop_sample) {
            dmc_sample_cur_addr = dmc_sample_start_addr;
            dmc_bytes_remaining = dmc_sample_len;
        }
        else
            if (dmc_irq_enabled) {
                dmc_irq = true;
                update_irq_status();
            }
    }
}