Fixing Nestest failiures
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Every instruction failed, so it's some instruction or behavior that's causing them all to fail. I noticed I hadn't uploaded a newer version of the test that's more robust to emulator errors like this. instr_test-v2. This uses a pre-computed CRC table and makes extra sure the APU IRQ is turned off, even if an emulator handles it wrong in some ways.
- comegordas
- Posts: 53
- Joined: Sat Aug 14, 2010 7:12 pm
Blargg, and what about this?
JMP ($02FF) = A900, and afther that the PC is at 0300, and not at A900. did i get wrong the indirect addressing mode?[/code]
Code: Select all
DB9E 8D 00 03 STA $0300 = 01 A:A9 X:07 Y:00 P:E5 SP:FB CYC:114 SL:63
DBA1 A9 AA LDA #$AA A:A9 X:07 Y:00 P:E5 SP:FB CYC:126 SL:63
DBA3 8D 01 03 STA $0301 = 00 A:AA X:07 Y:00 P:E5 SP:FB CYC:132 SL:63
DBA6 A9 60 LDA #$60 A:AA X:07 Y:00 P:E5 SP:FB CYC:144 SL:63
DBA8 8D 02 03 STA $0302 = 00 A:60 X:07 Y:00 P:65 SP:FB CYC:150 SL:63
DBAB 20 B5 DB JSR $DBB5 A:60 X:07 Y:00 P:65 SP:FB CYC:162 SL:63
DBB5 6C FF 02 JMP ($02FF) = A900 A:60 X:07 Y:00 P:65 SP:F9 CYC:180 SL:63
0300 A9 AA LDA #$AA A:60 X:07 Y:00 P:65 SP:F9 CYC:195 SL:63- comegordas
- Posts: 53
- Joined: Sat Aug 14, 2010 7:12 pm
Every ZP,X instruction does an 8-bit add, and wraps back to 00 if it exceeds FF. Hence why it's Zeropage,X. Same idea with Indirect,X addressing, it pulls the two address bytes entirely from within the zero page.
Some instructions have a one-cycle penalty for when computed addresses cross a 256-byte boundary (a 'page').
For example, lda 02FF,X takes one more cycle to execute if X >= 1, so it must adjust the high byte of the address.
Branch instructions (BNE, BEQ, etc) also have a penalty if the branch address target is on a different page than the address _after_ the branch instruction.
The document here lists what all the instructions do at each cycle:
http://nesdev.com/6502_cpu.txt
This document is also a nice summary for telling you which instructions have the cycle penalties (but has other errors, for example, is says that PLA doesn't affect flags when it does.)
http://www.masswerk.at/6502/6502_instruction_set.html
Some instructions have a one-cycle penalty for when computed addresses cross a 256-byte boundary (a 'page').
For example, lda 02FF,X takes one more cycle to execute if X >= 1, so it must adjust the high byte of the address.
Branch instructions (BNE, BEQ, etc) also have a penalty if the branch address target is on a different page than the address _after_ the branch instruction.
The document here lists what all the instructions do at each cycle:
http://nesdev.com/6502_cpu.txt
This document is also a nice summary for telling you which instructions have the cycle penalties (but has other errors, for example, is says that PLA doesn't affect flags when it does.)
http://www.masswerk.at/6502/6502_instruction_set.html
Here come the fortune cookies! Here come the fortune cookies! They're wearing paper hats!
- comegordas
- Posts: 53
- Joined: Sat Aug 14, 2010 7:12 pm
BTW, i'm having something strange with this rom. that tile "*" is not getting showed on my emulator, and i can't figure out why.
Nestest on FCEUX:

Nestest on my emulator:

i've loaded the rom in FCEUX and in VirtuaNES and then see what the Name Table Viewer shows, and in both emulators the tile "*" is marked as background data (not as sprite data). but anyway this tile doesn't shows up on my emulator as a background tile, neither as a sprite
Nestest on FCEUX:

Nestest on my emulator:

i've loaded the rom in FCEUX and in VirtuaNES and then see what the Name Table Viewer shows, and in both emulators the tile "*" is marked as background data (not as sprite data). but anyway this tile doesn't shows up on my emulator as a background tile, neither as a sprite