sd2snes

Hilmarf · Post by **Hilmarf** » Thu Apr 14, 2011 5:43 pm

Got myself a snes powerpak, but still...I'm interested to know if you will produce sd2snes units

ikari_01 · Post by **ikari_01** » Fri Jun 17, 2011 5:09 pm

Finished the uPD77C25 core. DSP1-4 work fine.

(DSPx roms required.)

There will probably be a first batch of 100 sd2sneses this year, maybe another 100 next year. Not so sure yet.

Near · Post by **Near** » Sat Jun 18, 2011 2:02 am

> Finished the uPD77C25 core. DSP1-4 work fine. Smile (DSPx roms required.)

Neat :D
Is there enough memory to support the ST-0010 and ST-0011? It needs 52KB instead of 8KB per game, but the instruction set is the same, just with a new jump mechanism.

If not, I believe we can get ST-0010 support in there by intentionally trimming the ROM (it's 90% padding) and treating it like a 7725 instead of a 96050. That game barely uses the chip at all.

Also, if you haven't stopped by my forum recently, we were able to RE the Hitachi HG51B169 (Cx4) for MMX2/MMX3. The program ROM is stored on the mask ROM, and you only need 0x1800 bytes for data RAM+data ROM. It does have a high clock rate though, 20MHz. May not be worth the work/FPGA space for only two games.

> There will probably be a first batch of 100 sd2sneses this year, maybe another 100 next year. Not so sure yet.

Awesome! Please save one for me to buy :D

mic_ · Post by **mic_** » Sat Jun 18, 2011 2:43 am

Awesome! Please save one for me to buy

+1 on that.

ikari_01 · Post by **ikari_01** » Sat Jun 18, 2011 3:50 am

Is there enough memory to support the ST-0010 and ST-0011? It needs 52KB instead of 8KB per game, but the instruction set is the same, just with a new jump mechanism.

Sadly no, the FPGA has roughly 36kB of block RAM. 17kB of those are always dedicated to MSU1 for data+sound buffers (MSU1 should be supported alongside any custom chips).

Now I could theoretically use both my external memory chips combined to fetch a 24bit instruction in a single cycle but I doubt I can get to 8MHz core clock with that (the SNES must access both buses quasi-simultaneously and one of the memory chips is only 70ns).

About the CX4 (AWESOME feat, read a lot about it!) - Doesn't it also have an internal program RAM where it copies one 512b "page" from the mask ROM prior to execution? Or does it fetch directly from mask ROM? How is SNES ROM access handled then? Or does it have a switch like the SuperFX?
I think I should read the source already...

Near · Post by **Near** » Sat Jun 18, 2011 4:16 am

Sadly no, the FPGA has roughly 36kB of block RAM.

Drat. Okay, if you want to try and get F1 ROC II running anyway ... try this.

Cut the first 6KB of the ST-0010 ROM to a new file, this will be the program ROM. Now go 48KB into the file, and copy the next 4KB into our new file. This will give you a 10KB file similar to the other dspN.bin files, only it'll use an extra 2KB of data ROM. See if F1 ROC II will run using your 7725 core @ 8MHz, I believe it will. It does not use any new opcodes, the only obvious thing is that it needs one extra bit on the data ROM pointer address.

st0010.bin only has 0x640 bytes of PROM, and 0xbe0 bytes of DROM.

Doesn't it also have an internal program RAM where it copies one 512b "page" from the mask ROM prior to execution? Or does it fetch directly from mask ROM? How is SNES ROM access handled then? Or does it have a switch like the SuperFX?

Yes. It has to buffer in the first page as well. You can load in pages from the SNES or Cx4 side. I don't know yet if the SNES side can load in both pages or just the primary/active one. I also don't know how the buffering works from the Cx4 side. My guess is the chip freezes until the buffering is finished.

The mask ROM is completely inaccessible to the SNES while buffering is under way. The Cx4 takes over the ROM chip to do its own buffering as needed. It doesn't appear that access is restored until the Cx4 hits a halt opcode. So you're pretty much fucked if it gets stuck in a loop I guess.

The Cx4 also has a simple DMA that can move mask ROM into Cx4 RAM. This also locks out the SNES CPU from accessing the ROM (and presumably the Cx4 RAM) while it is active.

And lastly, it allows vector override. Write new vectors into $7f60-7f, and when the Cx4 is active, it will give those values for $ffe0-ffff for NMI/IRQ support. MMX2/3 don't seem to use this feature, though. It just turns off all interrupts prior to executing a function.

-----

I do love the clock speed, the instruction set, and number of registers. But this chip honestly sucks compared to the uPD and SA-1 in terms of power. Having to multi-task out of work RAM is really shitty, and 256-instruction pages are much too small.

ikari_01 · Post by **ikari_01** » Sat Jun 18, 2011 11:18 am

Trying it out now.
Do I also need to map the data RAM?

Near · Post by **Near** » Sat Jun 18, 2011 6:10 pm

For the chip to function, no. It only communicates with the SNES via DR/SR, just like the DSP-n chips.

However, it does use the mapped data RAM area as non-volatile save RAM. Basically just map that in like regular cartridge SRAM and it should be fine.

ikari_01 · Post by **ikari_01** » Sun Jun 19, 2011 6:37 am

Hm, looks like it communicates exclusively via DP. I logged all dsp accesses in bsnes and DR/SR are not touched even once by F1 ROC II. However once the race starts, there's a firework on DP.
I guess I'll have to implement it then

ikari_01 · Post by **ikari_01** » Sun Jun 19, 2011 1:50 pm

ST0010 now works.

Had to up the DataRAM size from 256 to 1024 words and make it shared between the uPD and SNES.

Near · Post by **Near** » Sun Jun 19, 2011 3:03 pm

Ah, guess I was wrong after all. Sorry about that :(
Glad to hear that it works though, great job! I was hopeful you could get it to work, given how small the program ROM turned out to be.

We'll have to leave the ST-0011 to the emulators for now. That thing is a real beast, and you really need all 15MHz since it's a Chess AI.

ikari_01 · Post by **ikari_01** » Mon Jun 20, 2011 7:21 am

Evil idea:

The ST0011 program ROM uses only 410 different instruction words... so I could reduce the instruction size to 9 bits and use a LUT. Of course that's far from a universal approach.
It would still require cutting MSU1 support for ST0011 but it might be better than nothing (except, well, it's just some Shogi game

)

EDIT: ugh, disregard that... I counted only among the first 2048 instruction words.

Now there are 2139 different instructions.

Near · Post by **Near** » Mon Jun 20, 2011 9:22 am

More info on Cx4:

Cleaned source code @ snes/chip/hitachidsp in:
http://bsnes.googlecode.com/files/bsnes_v079r04.tar.bz2
(vector override portion is not used by MMX2/MMX3)

Hardware requirements:
0xc00 bytes data RAM aka IRAM
0xc00 bytes data ROM
~0x200 bytes registers and MMIO stuff

Technical requirements:
24-bit registers with 24-bit signed multiplication to 48-bit result
Roughly 32 or so unique opcodes, all very simplistic
Has a DMA mode that transfers from ROM to IRAM
Either the SNES or the Cx4 has control of the ROM/IRAM, never both
It's safe to always allow SNES ROM/IRAM access, so long as it won't stall out the Cx4
Program ROM is inside the game itself. You can either buffer in 2x512-byte pages, or fetch on demand. The former is more correct, but the latter works fine as well.
Wants to run @ 20MHz, but it can be safely under-clocked a good bit, from what I hear.

Anyway, it seems like you are well on your way here to an official release. I'm not suggesting you expend effort on Cx4 support or anything, unless you really want to.

But if you do want the chip support, let me know if I can be of any assistance :D

ikari_01 wrote:It would still require cutting MSU1 support for ST0011 but it might be better than nothing

Do you mean only that one game could not use ST0011+MSU1 at the same time? Or that you'd have to remove it entirely to support it? If the former, not a big deal. If the latter, ;_;

The first one's easy to get anyway if people really want to play it. But I mean there's probably two people in the world interested in playing it anyway. F1 ROC II on the other hand seems pretty popular, Lord Nightmare is a big fan of it.

EDIT: ugh, disregard that... I counted only among the first 2048 instruction words. :( Now there are 2139 different instructions.

ST-0011 is an absolute beast. The most powerful coprocessor (sans maybe the ST-0018), and utilized almost 100%. It also really wants to be run at 15MHz. You can probably get away with 8MHz, but AI moves would take twice as long. You'd have to hack the title screen to read "遅指し二段森田将棋" :P

ikari_01 · Post by **ikari_01** » Mon Jun 20, 2011 2:13 pm

Haha don't worry. I'd never ax MSU1 for one custom chip. If I had to decide I'd rather ditch ST0011 completely.

I meant disable MSU1 when ST0011 is used.

And of course I want to support Cx4. Mega Man X2/3 are essential IMO.
Even if I don't finish it now, sd2snes can flash itself from SD Card, so I'm expecting a variety of features to arrive after release anyway.

Anyway, thanks for all the details on the Cx4. It seems very nice to implement instruction architecture wise.

About the ST0011: I have the 7725 core running @13.71MHz (96/7) at the moment anyway, so 15MHz (would be 16MHz then) is probably not a far cry. However ST0011 doesn't have top priority now.
Also LOL @遅指し

Ah btw, how is the DataRAM split up with the ST0011? F1 ROC II seems to use the lower half of the ST0010's DataRAM for data exchange between the DSP and SNES, and the upper half for storing save data.

Near · Post by **Near** » Tue Jun 21, 2011 1:01 am

That's a good question. I'm afraid I haven't looked at Morita Shougi 1 any more than necessary to get it playable, heh. It's a very boring game.

The flashing thing sounds cool. Lots of potential there for Cx4, OBC1, S-DD1 (proper - for SFA2) and SPC7110; perhaps some entrepreneurs will take a stab at it for you, ala the Retrode's dumping adapters.