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kyuusaku wrote:The reason the first way didn't work is because you are enabling the 257 with /RD. /RD is asserted on every memory read so you are trashing the bus. In the other thread I used a 139 decoder to create an OR gate (/ROMSEL OR /RD) which is the proper condition. I think you could change around the MAD-1 connections to get this condition too since both ROM decoders aren't used with a single ROM, just replace the "select" address line input with /RD.

The transparent latch theory shows that /ROMSEL (and MAD-1 likely) will be asserted before /RD, I believe that's how it is.

Wow, I'm an idiot... I didn't realize I was enabling 74HC257 output bus in every memory access........................................................

Is there any time diagram around internet showing timing of these lines on the SNES? It could be useful to take a look at whenever I have a doubt about it, so I could save asking stupid questions like the one before :S

I'll try to do it in ASCII

Grrr, since the code tag is broken (isn't it supposed to use a monospaced font?):


Edit: I gave SlowROM the same treatment and there's over 20ns of headroom too.

GREAT!

Phi2 is the CPU clock, isn't it? So it can be 3.58MHz or 2.86MHz... I'm doing a simulation with Modelsim to add all those signals plus the 65C816's outputs.

EDIT 1: Acording to 65C816 datasheet, RWB is asserted at the same time that A0..A15, so your signal R//W should be aligned in time with A0..A15, shouldn't it?

Yup.

Yes probably, I wasn't sure when it was valid (this might be the opposite of the 6502). It should make no difference for /RD though unless /RD and /WR just followed R//W which wouldn't be right since when you use an external register or something it has to be triggered on the rising edge of /WR.

I still wonder if the data bus is buffered though. In the datasheet example they use a buffer which would add more delay. It can be tested by comparing the data bus @ rising edge of Phi2 with the bank address. Really a logic analyzer is needed to verify Nintendo's implementation.

Well, this is the result of my simulation; I assume 25 ns of delay on decoding each signal and 25 ns too on latch's propagation time.



As you can see, in FastROM read cycle, the maximum ROM time access is 124 ns.
I assume /RD and /WR are decoded directly from RWB, not using /ROMSEL in any way, but maybe I'm wrong...

I guess I'm not being clear, /RD and /WR are valid AFTER Phi2 is high (/RD = Phi2 NAND RWB), /RD and /WR must follow Phi2 (like the 6502) or memory couldn't be latched with /WR and /RD would conflict with the bank register. Also I think the address is valid around 50ns into Phi1 (I took WDC's delay and increased it for presumably an older CMOS process). There is much more headroom than 4ns and you don't have any MAD-1/decoding delay which can be over 40ns. Where you should be calculating the time is from MAD-1/whatever decoder to the falling edge of Phi2, and that period should be around 140ns.

kyuusaku wrote:I guess I'm not being clear, /RD and /WR are valid AFTER Phi2 is high (/RD = Phi2 NAND RWB), /RD and /WR must follow Phi2 (like the 6502) or memory couldn't be latched with /WR and /RD would conflict with the bank register.

Right! I forgot to add that condition

kyuusaku wrote: Also I think the address is valid around 50ns into Phi1 (I took WDC's delay and increased it for presumably an older CMOS process). There is much more headroom than 4ns and you don't have any MAD-1/decoding delay which can be over 40ns. Where you should be calculating the time is from MAD-1/whatever decoder to the falling edge of Phi2, and that period should be around 140ns.

What's Phi1? I was searching for that in 65C816's datasheet and didn't find it... Phi2 is the CPU clock pin, but couldn't find any other pin called "Phi1".
You're right about MAD-1 delay, but I did the simulation using all timings on datasheet, and it turned out what you see... I took into account data hold time, and that data is latched by the CPU on the falling edge of Phi2.

I re-run my simulation:



And these are the timings:



And these are the detailed timings:

PHI2 Falling Edge to Valid Address and Bank - tADS





Bank Latch Delay





/ROMSEL Propagation Delay





/RD Propagation Delay






Data Setup Time (to Phi2 Falling Edge) - tDSR






Data HoldTime (to Phi2 Falling Edge) - tDHR

Phi1 is the same as Phi2, inverted, so by it I mean the low period of Phi2.

Still in your diagram I think ROM data should be valid earlier. The /OE delay on a 120ns ROM I believe is 30ns max. Also I'm not sure why time is measured from /ROMSEL until data valid or what the 29ns is for. I think it's more clear from /ROMSEL to the falling edge of Phi2 because that represents the period for the address decoder and /CE to valid output delay, or the total cartridge propagation time. Looking at your diagram (with 75ns to valid address) it looks like there's ~155ns which is a little slim, only simple address decoders would work. I think it will be 170-190ns on the real thing.

kyuusaku wrote:Phi1 is the same as Phi2, inverted, so by it I mean the low period of Phi2.

Ok, thanks

kyuusaku wrote: Still in your diagram I think ROM data should be valid earlier. The /OE delay on a 120ns ROM I believe is 30ns max.

I didn't take that into account because /RD is asserted far before that data is accessed on MaskROM, since the MaskROM output is enabled 30ns after /RD (assuming /RD is connected directly to ROM's /OE).

kyuusaku wrote: Also I'm not sure why time is measured from /ROMSEL until data valid or what the 29ns is for.

Because I assume there is not any MAD-1 or address decoder between /ROMSEL and ROM's /CS. ROM data is valid 120ns after /ROMSEL is asserted (assuming 120ns time access for the MaskROM), and it MUST be valid 29ns before PHI2 falling edge so the CPU can latch/register those data. 29ns is the setup data, therefore.

kyuusaku wrote: I think it's more clear from /ROMSEL to the falling edge of Phi2 because that represents the period for the address decoder and /CE to valid output delay, or the total cartridge propagation time. Looking at your diagram (with 75ns to valid address) it looks like there's ~155ns which is a little slim, only simple address decoders would work. I think it will be 170-190ns on the real thing.

You can't measure from /ROMSEL (that is when MaskROM is enabled) to falling edge of PHI2 because of tDSR... Data must be valid "tDSR" ns (setup time) before the falling edge of PHI2.

Maybe the problem with my diagram is that propagation time is too high. I assumed 74LSXXX standard delays for decoding signals but that is not true. Probably, combinational delays are less than 25 ns since combinational logic is embedded on the same chip...

Oh I see, well I think the data bus is Hi-Z from a few ns after Phi1 until 30ns after (/CE OR /RD) == 0. From that moment until /CE is asserted for 120ns there is invalid data on the bus, but there's still something.

I don't think there's a 30ns setup time for the internal latching, 5ns seems more in line (74HC), but the WDC datasheet says 10ns (@ 5V, I think you're looking at 2.5V). I guess it does matter, I just wrote it off before as negligible with the other setups.

kyuusaku wrote:Oh I see, well I think the data bus is Hi-Z from a few ns after Phi1 until 30ns after (/CE OR /RD) == 0. From that moment until /CE is asserted for 120ns there is invalid data on the bus, but there's still something.

Maybe the data is present but invalid, I don't know... but I prefer to simulate it as Hi-Z to make the diagram easier to understand.

kyuusaku wrote:I don't think there's a 30ns setup time for the internal latching, 5ns seems more in line (74HC), but the WDC datasheet says 10ns (@ 5V, I think you're looking at 2.5V). I guess it does matter, I just wrote it off before as negligible with the other setups.

Aboslutely right, I made a big mistake: I was looking at 2.5V, since I read on the top of the column "4 MHz", but the right one is the first, the one with data for 5V:



I'll redo all simulations to match those parameters

EDIT:

The new simulation with the proper timings:



Time from /ROMSEL to ROM's output data is much longer now: more than 200 ns, and assuming there is a MAD-1 decoder on the cartridge, you get more than 170 ns from ROM /OE (from MAD-1) to ROM's output data. I assumed 33 ns delay for MAD-1.

And there is one interesting conclusion (if there is no mistake in the simulation): time from /RD to ROM's data output is 115ns, which would explain that my repros worked using /RD as EPROM's /CS instead of EPROM's /OE...