VRC-VI multicart

[Haruka]

Now I understand how to use 74'32. Why not power 74'32 with +5V, and pull 62256's /CE to +3V of battery through a big res(e.g. 100k)? This eliminates the power consumption of 74'32 when cart is not working.

[l_oliveira]

Just don't forget to supply 7432 from the battery aswell and use CMOS variant (74HC/74HCT), not the TTL (LS/F)

What I did with the normal 74LS32 defeats the need of using special low power logic and reduces consumption from the battery. the MN1026 has inverted and non inverted outputs.

Edit: Just to make sure everyone understands, on my cart the 74LS32 is powered from the regular 5V rail.

[l_oliveira]

Now I understand how to use 74'32. Why not power 74'32 with +5V, and pull 62256's /CE to +3V of battery through a big res(e.g. 100k)? This eliminates the power consumption of 74'32 when cart is not working.

The purpose of the MN1026 IC is control the SRAM power consumption from the battery and make sure it's always disabled/sleeping when power in unstable (power on and power off cycles). If you remove it, the data in the RAM will corrupt a lot easier than it would normally.

It would be of your interest keep the MM1026 even while using the FRAM as it might keep the FRAM from receiving unwanted pulses during power up/off.

[Haruka]

I also noticed the difference between SRAM and FRAM. So I searched the net and found the following circuit.

This circuit has been tested on my namco163 flashcart
and worked fine.
But on VRC6, something weird happens. If the game(bootloader for the VRC6 multicart) never enables WRAM (i.e. $B003.7 = 0), the game works fine. Other games(Esper dream 2 and Mouryou Senki MADARA) enable and access WRAM at the beginning of the games, then they crash.
However if I disable the WRAM by polling /CE high, all games work like a charm. Althrough they will lock up at the loading profile screen due to the absence of WRAM.

[l_oliveira]

What you do with the /WE signal of the FRAM? connect straight to R/W?
Connected like this, right?
CE# = /WRAM_CE coming from mapper logic.
OE# = GND?
WE# = R/W?

[Haruka]

What you do with the /WE signal of the FRAM? connect straight to R/W?
Connected like this, right?
CE# = /WRAM_CE coming from mapper logic.
OE# = GND?
WE# = R/W?

Well, yes.
To make things clear, let me explain more.

Actually I made a little adapter from the circuit I posted previously.

As you can see, it is pin-compatible with 62256, and works like a non-volatile 62256.
So,
FRAM./WE = Adapter./WE
FRAM./OE = Adapter./OE
FRAM./CE = (Adapter./WE NAND Adapter./OE) NAND (NOT Adapter./CE)

Then I mounted the adapter on the cart, replaced the WRAM.
So,
Adapter./WE = WRAM./WE
Adapter./OE = WRAM./OE
Adapter./CE = WRAM./CE

As for WRAM, MM1026 is removed together with battery. So WRAM.+CE is not used anymore.
And from the route on the PCB,
WRAM./WE = CPU.R/W
WRAM./OE = GND
WRAM./CE = deglitcher.output

[Haruka]

I bought some chips and made a test.
I used a 74'139 to decode WRAM access, completely bypassed WRAM /CE pin on VRC6. The result is still a failure. It proves that the VRC6 itself is not damaged. There must be somewhere other than VRC6 that caused the weird problem.

[Haruka]

This is what the 74LS32 is doing on that cart (might not be wired physically like this on my cart as I just drew this from my head).
The circuit below is meant to make up to the fact that 62256s have no non-inverted Chip Enable pin.

VRC6_32KWRAM.PNG

The second OR gate is useless, isn't it? Connect WRAM's /OE directly to VRC6's WRAM /CE(after the deglitcher) is still working, right?

And the first OR gate can be replaced with two diodes and one resistor to save a chip. Am I correct?

[lidnariq]

I used a 74'139 to decode WRAM access, completely bypassed WRAM /CE pin on VRC6. The result is still a failure. It proves that the VRC6 itself is not damaged.

If, for some reason, it is a bus conflict, it could indicate that the VRC6 is enabling the ROM when it shouldn't.

The second OR gate is useless, isn't it?

It adds some propagation delay. No idea if if matters; certainly the datasheet for the FM18W08 strongly implies it should be safe to ground /OE.

And the first OR gate can be replaced with two diodes and one resistor to save a chip. Am I correct?

Diode-OR logic loads the input signals; I'd recommend using a BJT-based OR gate if you want to avoid buying a 74'1g32.

[l_oliveira]

This is what the 74LS32 is doing on that cart (might not be wired physically like this on my cart as I just drew this from my head).
The circuit below is meant to make up to the fact that 62256s have no non-inverted Chip Enable pin.

VRC6_32KWRAM.PNG

The second OR gate is useless, isn't it? Connect WRAM's /OE directly to VRC6's WRAM /CE(after the deglitcher) is still working, right?

And the first OR gate can be replaced with two diodes and one resistor to save a chip. Am I correct?

In the case of the 62256 you cannot put the /OE straight to GND because /CE will be always low when the power is on, /OE and /WE become your only mean of disconnecting the chip from the BUS. Then no, you cannot get rid of both OR ports.

Edit: As I mentioned on a previous post, the point of the OR ports is control the BUS without using the /CE pin which then is connected directly to the SRAM watchdog circuit. That way there is no need to have anything else connected to the VBAT rail, just the SRAM and the watchdog IC.