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Questions on Wiring 32Mb TSOP Flash
Posted: Fri Sep 02, 2011 8:55 pm
by bazz
Hi guys + gals.. First off I'd like to thank everyone for making this website + forum so awesome. I have been visiting for years, but only now have I finally registered an account xD
So I am in the process of receiving the parts to make a custom flash cartridge out of Mario Paint, I will be using my own TSOP adaptor with AM29F032B which I originally made for hacking my Gameboy Cartridge.... I later stumbled on RomLab's TSOP adapter for SNES cartridges and exclaimed, since I had to order 3 duplicates of the board anyways!! Now I have a reason to use the others
Please I need help in understanding the Address Decoder 74LS139 and any possible adjustments necessary when incorporating the FLASH. in getting to understand the decoder, I was looking at Super Mario World's configuration:
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Address Decoder 74LS139 Pinout (SUPER MARIO WORLD)
__ __
SNES #49 |01\/16| +5V
A21 |02 15| NC
A20 |03 14| A19
ROM /OE |04 13| RESET
NC |05 12| NC
NC |06 11| NC
NC |07 10| NC
GND |08 09| RAM /CE
------
I was led to many questions,How are those address lines being used exactly?? must I make accomodations so I can use my FLASH A19-21 ?? or do I just go ahead and plug FLash A19-A21 to the cart connector... I am saying these thoughts out loud so you may help me understand how the effin thing works.. BUT the ultimate question is simply.
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What adjustments must I make to the cartridge (+decoder) when adding 32Mbit flash?
I realize that with Super Mario World it is not a 36-pin DIP ROM, so perhaps the Mario Paint will have a different method (if it is 36-pin DIP?!??!?!?) I selected Mario Paint because it has BIG SRAM, and I read elsewhere on this forum that 32mb flash can go in there...
EDIT: and it IS 32-pin-DIP mask rom...
http://www.snescentral.com/pcb.php?id=0 ... side=front
I feel very in the dark about these things, please help me understand. Thank you :]
Posted: Sat Sep 03, 2011 1:24 am
by infiniteneslives
Have you checked out the datasheet to understand how the decoder/demux is designed?
http://pdf1.alldatasheet.com/datasheet- ... LS139.html Check the truth table on page 4.
Also checking my Mario paint you've got an error (missing information) in your pinout. Pin 7 is connected to pin 15 (and nowhere else).
Decoders basically convert a binary number to "one hot" in this case the outputs are inverted. You've got two separate 2to4 decoders split by the left and right side.
I'm not speaking from SNES experience, just logically.
For this set up you've got A21 and A20 as inputs to the left side. When they are both low and enabled (SNES #49 low) then the ROM /OE will be low, otherwise it's high. Similarly pin 7 will be low whenever A21 and A20 are high. Which then feeds into the right circuit and you've got similar performance with those signals.
But if all you're doing is changing the ROM to flash (and RAM to flash?) the only thing controlled by the '139 is the enable signals which shouldn't any different except pinout.
Posted: Sat Sep 03, 2011 9:06 am
by bazz
infiniteneslives wrote:Have you checked out the datasheet to understand how the decoder/demux is designed?
Yes I have. It is not that I do not understand the decoder, it is that I see here we have a cartridge that has no ROM A20+21... My knowledge of electronics is not so good, you can help me here, because I interpret it as the SNES is driving A20 A21 to the decoder, and i have feelings that if I attach Flash ROM A20+A21 into the situation that it will disrupt whatever communication is going on already on these lines!! I have strong feelings you will finally clarify my clouded view of how address lines work etc. See I only have really seen this stuff working on my gameboy cart recently (i made a 4m flash cart), it required no real tech. understanding.. Now I need to and want to understand WTF is going on.. so I understand correctly.
Also checking my Mario paint you've got an error (missing information) in your pinout. Pin 7 is connected to pin 15 (and nowhere else).
My pinout is actually for Super Mario World.. EDIT: i was wrong they have the same pinout, my bad![/quote]
But if all you're doing is changing the ROM to flash (and RAM to flash?) the only thing controlled by the '139 is the enable signals which shouldn't any different except pinout.
andd RAM to flash?? I was planning on simply replacing the ROM and keep/use the RAM. I am wondering why you would recommend this?
Aside from the explanation I am hoping you will give me on address lines and how this shit all works together, the end solution seems to be plug and play?? as long as I attach correct pins from AM29->Mask ROM pins, and including A22, I should be good??
Posted: Sat Sep 03, 2011 11:54 am
by MottZilla
Find a SNES game with a 36 pin DIP maskrom. Replace with Flash memory. You're done. There are SNES Mask ROMs with fewer than 36 pins which means the maximum ROM size it was designed for is less than what you want for 32Mbits.
Posted: Sat Sep 03, 2011 2:10 pm
by bazz
MottZilla, while that would be the best for plug and play, I already purchased a Mario Paint (32-pin maskrom) cart, and this forum post states that it should work
http://nesdev.com/bbs/viewtopic.php?t=4 ... ario+paint
Posted: Sat Sep 03, 2011 3:50 pm
by infiniteneslives
Any SNES board *could* work. Some would just require more conversion then the others. If you really want to stick with the mario paint I would recommend finding or drawing out the schematics for the two boards so you'll know what traces you'll have to modify to convert the cart.
If the flash your adding is bigger than the mario paint ROM then you'll have to figure out how the upper bits should connect up to the decoder. My guess is you'll have some connecting to the NC pins on the decoder. But this is all speculation as my SNES mapper knowledge is weak to non-existent.
Posted: Sun Sep 04, 2011 11:22 am
by bazz
Let's look more at Super Mario World..
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Address Decoder 74LS139 Spec. (two independent decoders in chip)
__ __
1G |01\/16| +5V
1A |02 15| 2G
1B |03 14| 2A
1Y0 |04 13| 2B
1Y1 |05 12| 2Y0
1Y2 |06 11| 2Y1
1Y3 |07 10| 2Y2
GND |08 09| 2Y3
------
--------------------------------------
| INPUTS | OUTPUTS |
| ENABLE | SELECT | |
| G | A B | Y0 Y1 Y2 Y3 |
--------------------------------------
| H | X X | H H H H |
| L | L L | L H H H |
| L | H L | H L H H |
| L | L H | H H L H |
| L | H H | H H H L |
--------------------------------------
Address Decoder 74LS139 Pinout (SUPER MARIO WORLD)
__ __
SNES #49 |01\/16| +5V
A21 |02 15| NC
A20 |03 14| A19
ROM /OE |04 13| RESET
NC |05 12| NC
NC |06 11| NC
NC |07 10| NC
GND |08 09| RAM /CE
Pins #07, #15 connected together (NC)
Click here, easier on the eyes ->
https://docs.google.com/document/d/1uHZ ... t?hl=en_US
A20 and A21 are not connected to ROM.
SNES#49 (OE) goes low -> check A21A20 (always low or high??) -> ROM /OE
Is this right?? I am not seeing the role that A20 and A21 play here, if there are no ROM address lines...
2G is a NC, which means it is also always high??? low?? unless A20 A21 are high together and SNES#49, then 7 goes low and is connected to 15, which goes low.. And now I must see the relationship between A19, RESET, and RAM chip enable?? WTF??
AH RIPS HAIR
Posted: Sun Sep 04, 2011 9:56 pm
by bazz
forget all the crap I said above.. I am beginning to understand... the outputs of the decoder are kept inverted tho, right? meaning that the results are used directly.... yeah it seems so...
Posted: Sun Sep 04, 2011 11:13 pm
by bazz
SNES #49 - (Assert /OE?)
(ROM /OE High DISABLES output)
A21 - L
A20 - L
ROM ENABLED, 2nd decoder disabled
A21 - H
A20 - L
ROM Disabled,2nd decoder disabled
A21 - L
A20 - H
ROM Disabled,2nd decoder disabled
A21 - H
A20 - H
ROM Disabled, 2nd decoder ENABLED
2nd ENCODER
-------------
Enabled when A21 and A20 are High, also disabling ROM output
(Reset is true when Low) - so you know decoder will not enable RAM when LOW
A19 - L
RESET - L
Ram Disabled
A19 - H
RESET - L
RAM Disabled
A19 - L
RESET - H
Ram Disabled..
A19 - H
RESET - H
RAM ENABLED!!!
Ok so with all this, I say to myself, How does a device like SNES try to read ROM etc? I realize now my biggest necessity is to understand this so I can see how it is using high Address lines in the decoder that are unused by the small ROM... I also do not understand why the 2nd decoder uses A19 in determining to enable the RAM chip, since it already knows the ROM is disabled by 2nd decoder being activated!! so wtf??
Posted: Sun Sep 04, 2011 11:42 pm
by bazz
OMG I AM GETTING IT GUYS!!!
So the reason why this check happens is because in the LoROM model, SRAM occurs at $70:0000 and you convert that to binary and get BITS SET AT A19, A20, and A21 !!! So all the FACKEN DECODER does is line up the model!!! OMGGGGGGGGGGG lol
:]
Posted: Mon Sep 05, 2011 12:22 am
by infiniteneslives
Glad to see you were able to make sense of it all
I've had some similar confusion about mappers on the NES. Like your figuring out you need to understand the address map before you try to make sense of why the logic of a mapper is set up the way it is.
Posted: Mon Sep 05, 2011 1:22 am
by bazz
ha, cept i just realized that $70:0000 is actually bits A22,A21,A20 set... so now why would that be....why is RAM chip enabled at $38:0000?? Yet again I feel I am missing something -.-
EDIT: FUCK YEAH.. I took a closer look at MY OWN Super Mario World, and A22 is actually the DECODER pin 2. FUCK YEAH lol
EDIT 2: shit.. I dont know what to believe.. take a look....
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+--------+
21.477MHz Clock | 1 32 | /WRAM
EXPAND | 2 33 | REFRESH
PA6 | 3 34 | PA7
/PARD | 4 35 | /PAWR
GND | 5 36 | GND
F A11 | 6 37 | A12
r A10 | 7 38 | A13
o A9 | 8 39 | A14
n A8 | 9 40 | A15
t A7 | 10 41 | A16
A6 | 11 42 | A17
o A5 | 12 43 | A18
f A4 | 13 44 | A19
A3 | 14 45 | A20
c A2 | 15 46 | A21
a A1 | 16 47 | A22
r A0 | 17 48 | A23
t /IRQ | 18 49 | /CART
D0 | 19 50 | D4
D1 | 20 51 | D5
D2 | 21 52 | D6
D3 | 22 53 | D7
/RD | 23 54 | /WR
CIC out data (p1) | 24 55 | CIC out data (p2)
CIC in data (p7) | 25 56 | CIC in clock (p6)
/RESET | 26 57 | CPU_CLOCK
Vcc | 27 58 | Vcc
PA0 | 28 59 | PA1
PA2 | 29 60 | PA3
PA4 | 30 61 | PA5
Left Audio Input | 31 62 | Right Audio Input
+--------+
versus
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---+---
GND |05 | 36| GND
A11 |06 | 37| A12
A10 |07 | 38| A13
A9 |08 | 39| A14
A8 |09 | 40| NC or to MAD-1 Decoder pin #15
A7 |10 | 41| A15
A6 |11 | 42| A16
A5 |12 | 43| A17
A4 |13 | 44| A18
A3 |14 | 45| A19
A2 |15 | 46| A20
A1 |16 | 47| A21
A0 |17 | 48| A22
/IRQ |18 | 49| /OE
D0 |19 | 50| D4
D1 |20 | 51| D5
D2 |21 | 52| D6
D3 |22 | 53| D7
/CE |23 | 54| /WE
Pin 1 D413 |24 | 55| Pin 2 D413
Pin 7 D413 |25 | 56| Pin 6 D413
RAM /E |26 | 57| NC
VCC |27 | 58| VCC
---+---
I trust the top 1 because it's newer AND it would make since that PIN40 is A15 which is NC on LOROM :]
Posted: Mon Sep 05, 2011 2:43 am
by bazz
Here it is corrected.. And now I know the adjustments I need to make..
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Address Decoder 74LS139 Pinout (SUPER MARIO WORLD)
__ __
SNES #49 /CART |01\/16| +5V
A22 |02 15| (7)
A21 |03 14| A20
/ ------- |04 13| RESET
ROM /OE <----AND------- |05 12| NC
\ ------- |06 11| NC
(15) |07 10| \---AND--> ROM /OE
GND |08 09| RAM /CE
Pins 4,5,6,10 all collectively go into a DUAL AND Logic Gate, meaning that if ROM /OE ever has an instance of being low, IT WILL BE SET LOW, the gate will turn all other HIGH signals to lows..
ROM /OE only appears once on the second decoder because we can only enable ROM when we are not resetting AND not using A20.. or we can use the RAM chip / do nothing (reset).
The addition of the Gate was necessary, before the addition, whenever either A22 or A21 was set, the ROM output would become disabled.. SMW had a small ROM size of 4Mbit -> only 16 32K banks..... so they could do this.. But This logic gate fix allows the ROM to continue being enabled for all Addresses using A22-A20 address bits.
This effectively enables Mapping of ROM from $10:0000->$7F:0000!! And of course it will be mirrored in banks $80-$FF.
My next wonder is that if I wire my flash rom pin A15, I will be able to get ROM on $0000-$FFFF on any banks $40-$7D instead of only mirrored $8000-$FFFF
Posted: Mon Sep 05, 2011 7:24 am
by tepples
bazz wrote:My next wonder is that if I wire my flash rom pin A15, I will be able to get ROM on $0000-$FFFF on any banks $40-$7D instead of only mirrored $8000-$FFFF
That's HiROM, right?
Posted: Mon Sep 05, 2011 11:16 am
by bazz
It wouldn't quite be HiRom or LoRom.. afaik
I want to talk about another component I found on the Cartridge.. It seems to be a PNP transistor (guessing, but it only makes sense),
I haven't drawn a schematic, but excluding a couple resistors and a diode, it looks like this:
TRANSISTOR
--------
base -> A21
collector -> RAM /CS
Emitter -> DECODER Pin#15
don't connect RAM /CS to the decoder unless A21 is High, that is what this is doing??? but it's like Why????
Why bother with this if the decoder has already checked if A21 as well as A22+A20 are high?? We should be good to go already...