SNES Board Labels
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Great Hierophant
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SNES Board Labels
Having looked at many, many boards, I can say with reasonable confidence that they are labeled consistently.
SHVC-1A1B-04 - What does this mean?
SHVC - ROM Manufactured by Nintendo
1 - 1 ROM Chip
A - LoROM
1 - 16KB SRAM
B - 74LS139 SRAM Decoding
04 - Board Revision
I present a list of ordinary boards found in licensed cartridges. No special chips or prototypes present :
MAXI-1A0N-30-2
MJSC-1J0N-20-2
SHVC-1A0N-01
SHVC-1A0N-02
SHVC-1A0N-10
SHVC-1A0N-20
SHVC-1A0N-30
SHVC-1A1B-01
SHVC-1A1B-04
SHVC-1A1B-05
SHVC-1A1B-06
SHVC-1A1M-01
SHVC-1A1M-11
SHVC-1A1M-20
SHVC-1A3B-11
SHVC-1A3B-12
SHVC-1A3B-13
SHVC-1A3B-20
SHVC-1A3M-10
SHVC-1A3M-20
SHVC-1A3M-21
SHVC-1A3M-30
SHVC-1A5B-04
SHVC-1A5M-01
SHVC-1A5M-11
SHVC-1A5M-20
SHVC-1J0N-10
SHVC-1J0N-20
SHVC-1J1M-11
SHVC-1J1M-20
SHVC-1J3B-01
SHVC-1J3M-01
SHVC-1J3M-01
SHVC-1J3M-11
SHVC-1J3M-20
SHVC-1J5M-20
SHVC-2A0N-01
SHVC-2A0N-10
SHVC-2A0N-11
SHVC-2A3M-10
SHVC-2A3M-11
SHVC-2J0N-01
SHVC-2J0N-11
SHVC-2J3M-01
SHVC-3J0N-01
SHVC-3J3M-01
SHVC-BA1M-01
SHVC-BA3M-10
SHVC-BA5M-10
SHVC-BJ0N-01
SHVC-BJ1M-10
SHVC-BJ1M-20
SHVC-BJ3M-10
SHVC-BJ3M-20
SHVC-YA0N-01
SHVC-YJ0N-01
Here is the key to the board labels :
SHVC - Nintendo Made Chips
MAXI - Majesco Sales Made Chips
MJSC - Majesco Sales Made Chips
1 - 1 ROM Chip (32 or 36-pin)
2 - 2 ROM Chips (32-pin) (with 74LS00 or MAD-1 Decoder)
3 - 3 ROM Chips (32-pin) (with 74LS139 and/or MAD-1 Decoder)
B - 2 ROM Chips (36-pin) (with 74LS00 or MAD-1 Decoder)
Y - 2 ROM Chips (32-pin) (with 74LS00 Decoder)
A - LowROM
J - HighROM
1 - 16KB SRAM (24-pin)
3 - 64KB SRAM (28-pin)
5 - 256KB SRAM (28-pin)
Note : SRAM is always battery backed in ordinary boards
N - No SRAM Decoding (may have 74LS00 for 2 ROMs or 74LS139 for 3 ROMs)
B - 74LS139 SRAM Decoding
M - MAD-1 SRAM Decoding
SHVC-1A1B-04 - What does this mean?
SHVC - ROM Manufactured by Nintendo
1 - 1 ROM Chip
A - LoROM
1 - 16KB SRAM
B - 74LS139 SRAM Decoding
04 - Board Revision
I present a list of ordinary boards found in licensed cartridges. No special chips or prototypes present :
MAXI-1A0N-30-2
MJSC-1J0N-20-2
SHVC-1A0N-01
SHVC-1A0N-02
SHVC-1A0N-10
SHVC-1A0N-20
SHVC-1A0N-30
SHVC-1A1B-01
SHVC-1A1B-04
SHVC-1A1B-05
SHVC-1A1B-06
SHVC-1A1M-01
SHVC-1A1M-11
SHVC-1A1M-20
SHVC-1A3B-11
SHVC-1A3B-12
SHVC-1A3B-13
SHVC-1A3B-20
SHVC-1A3M-10
SHVC-1A3M-20
SHVC-1A3M-21
SHVC-1A3M-30
SHVC-1A5B-04
SHVC-1A5M-01
SHVC-1A5M-11
SHVC-1A5M-20
SHVC-1J0N-10
SHVC-1J0N-20
SHVC-1J1M-11
SHVC-1J1M-20
SHVC-1J3B-01
SHVC-1J3M-01
SHVC-1J3M-01
SHVC-1J3M-11
SHVC-1J3M-20
SHVC-1J5M-20
SHVC-2A0N-01
SHVC-2A0N-10
SHVC-2A0N-11
SHVC-2A3M-10
SHVC-2A3M-11
SHVC-2J0N-01
SHVC-2J0N-11
SHVC-2J3M-01
SHVC-3J0N-01
SHVC-3J3M-01
SHVC-BA1M-01
SHVC-BA3M-10
SHVC-BA5M-10
SHVC-BJ0N-01
SHVC-BJ1M-10
SHVC-BJ1M-20
SHVC-BJ3M-10
SHVC-BJ3M-20
SHVC-YA0N-01
SHVC-YJ0N-01
Here is the key to the board labels :
SHVC - Nintendo Made Chips
MAXI - Majesco Sales Made Chips
MJSC - Majesco Sales Made Chips
1 - 1 ROM Chip (32 or 36-pin)
2 - 2 ROM Chips (32-pin) (with 74LS00 or MAD-1 Decoder)
3 - 3 ROM Chips (32-pin) (with 74LS139 and/or MAD-1 Decoder)
B - 2 ROM Chips (36-pin) (with 74LS00 or MAD-1 Decoder)
Y - 2 ROM Chips (32-pin) (with 74LS00 Decoder)
A - LowROM
J - HighROM
1 - 16KB SRAM (24-pin)
3 - 64KB SRAM (28-pin)
5 - 256KB SRAM (28-pin)
Note : SRAM is always battery backed in ordinary boards
N - No SRAM Decoding (may have 74LS00 for 2 ROMs or 74LS139 for 3 ROMs)
B - 74LS139 SRAM Decoding
M - MAD-1 SRAM Decoding
Hi, I'm missing the following pcbs from my collection any chance you can post photos?
SHVC-BA5M-10
SHVC-3J3M-01
SHVC-BA5M-10
SHVC-3J3M-01
Now that it's on here and not a random forum though most people will find it. I know I never found it when I searched before.rkrenicki wrote:This, we already knew. Sorry.
http://forums.no-intro.org/viewtopic.ph ... 41&start=0
I wonder what determines the # of ROM chips in the cart.
For the NES I think only one licenced game uses two 128k (1 Mbits) ROMs to make up 256k (2 Mbits) PRG-ROM and it was an early MMC1 games so probably 256k ROMs weren't common yet.
Use multiple ROMs are also probably the only way to have total ROM sizes which aren't power of 2 - although I have a Tactics Ogre cart which is 1A3M but yet the dumped ROM appears to be 3MB (24 Megabits) so either it's some kind of overdump or they managed to have multiple "ROMs" in a single chip that didn't sum to a power of 2 in total.
Another thing which is interesting is that the japanese version of Secret of Mana is 1J3B while the PAL version is 1J3M - both have 2MB (16 Megabits) Roms. So I guess more recent carts used the MAD chip while older used the LS chips.
For the NES I think only one licenced game uses two 128k (1 Mbits) ROMs to make up 256k (2 Mbits) PRG-ROM and it was an early MMC1 games so probably 256k ROMs weren't common yet.
Use multiple ROMs are also probably the only way to have total ROM sizes which aren't power of 2 - although I have a Tactics Ogre cart which is 1A3M but yet the dumped ROM appears to be 3MB (24 Megabits) so either it's some kind of overdump or they managed to have multiple "ROMs" in a single chip that didn't sum to a power of 2 in total.
Another thing which is interesting is that the japanese version of Secret of Mana is 1J3B while the PAL version is 1J3M - both have 2MB (16 Megabits) Roms. So I guess more recent carts used the MAD chip while older used the LS chips.
Useless, lumbering half-wits don't scare us.
I'd bet good odds that a different production run of the game was released with two ICs.Bregalad wrote:Use multiple ROMs are also probably the only way to have total ROM sizes which aren't power of 2 - although I have a Tactics Ogre cart which is 1A3M but yet the dumped ROM appears to be 3MB (24 Megabits) so either it's some kind of overdump or they managed to have multiple "ROMs" in a single chip that didn't sum to a power of 2 in total.
It's true, but the game had to developed using some combination of PROMs or RAM in the first place, and I suspect that it was probably easier and may have not been enough of a cost savings to warrant modifying the column or row decoders of the CMOS ROM.MottZilla wrote:I'm pretty sure 'non power of 2' MaskROMs are no problem at all. Lots of games are 10 megs or 12 megs or 24 megs and just have 1 single MaskROM. But EPROMs and Flash typically won't come in such sizes as we know.
(At best, for a 10Mbit game, you're talking about a die shrink to 63% — it's probably less, in practice — and you have to assume that being able to get 160% of games for the same amount of initial silicon isn't drowned out by the fixed costs (e.g.package) or counteracted by the up-front cost (now you need more engineer time to cut out unneeded parts)
I'm not sure what you mean. Given that the same bunch of manufacturers were making the MaskROMs the "cost" of making ROM sizes of 10, 12, 20 and 24 mbits was probably none. Maybe it was something when games were first getting bigger, for example Donkey Kong Country was 32 megs and actually contained two 16 meg chips. But other games, atleast those that were released later on like Ninja Gaiden Trilogy which I think was 1994 or 1995, are only 12 megs but used just 1 MaskROM. I've checked.
Really why would it cost more to just leave stuff out? That makes no sense. If anything it's cheaper.
Street Fighter 2 Turbo uses two ROM chips to reach 20 megabits. I would guess at this time making a single 20 megabit chip would have been more costly.
So for Tactics Ogre if 1A3M means 1 ROM chip, it's very likely correct. If the game came out later enough (which I think it did) making a single 24M MaskROM was no big deal.
Really why would it cost more to just leave stuff out? That makes no sense. If anything it's cheaper.
Street Fighter 2 Turbo uses two ROM chips to reach 20 megabits. I would guess at this time making a single 20 megabit chip would have been more costly.
So for Tactics Ogre if 1A3M means 1 ROM chip, it's very likely correct. If the game came out later enough (which I think it did) making a single 24M MaskROM was no big deal.
I was guessing that it might have something to do with the one-time ASIC design cost to make a 10, 12, 20, or 24 Mbit mask ROM when it'd have the same number of pins as a 16 or 32 Mbit mask ROM, of which the latter is more popular. But then if there's any sort of discount for a 10 vs. a 16 or a 20 vs. a 32, the volume might have made it up.MottZilla wrote:Really why would it cost more to just leave stuff out? That makes no sense. If anything it's cheaper.
Right; what did it cost to make a mask ROM in the early 90s? It cost some amount of money
And yes, once you've designed one 10mbit ROM mask with the same fabrication facility, or if you own the physical mask, the up-front costs of making a new identically-sized non-power-of-2-sized game should be the same as making a new power-of-2-sized game.
All I'm really saying is, there's a cheapest manufacturing technology for any given size of production run, whether it's (E)EPROM, PROM, two ROMs, one ROM with the data mirrored, or one non-square ROM with the row decoders modified.
- to design a mask (one time cost)
- to buy the silicon wafer, expose it, and cut it into dice (cheaper per die with smaller dice)
- package the dice, and populate the PCBs
- in salary for whoever's managing the production run.
And yes, once you've designed one 10mbit ROM mask with the same fabrication facility, or if you own the physical mask, the up-front costs of making a new identically-sized non-power-of-2-sized game should be the same as making a new power-of-2-sized game.
All I'm really saying is, there's a cheapest manufacturing technology for any given size of production run, whether it's (E)EPROM, PROM, two ROMs, one ROM with the data mirrored, or one non-square ROM with the row decoders modified.
