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Posted: **Thu Dec 22, 2011 3:27 pm**

Please help me to remake this cartridge :

Needed parts :
AX5202p for MMC3
29F040 for PRG
29F040 for CHR
74LS174
74LS157
Resistor (?)
Capacitor (?)
Diode (?)

Professor Kevin Horton wrote:What Is It?

Another MMC3-based multicart. Has 4 MMC3 games on it.
The Games:

Master Fighter 3 (StreetFighter clone), Bubbce Bobbce 2 (Bubble Bobble 2), Gun-Nac, and Zen Ninja (Zen: The Intergalactic Ninja).

The Tech:

Has a pirate MMC3 (marked "AX5202P" on the chip) and some misc. TTL logic to map in the game select register.

--------------------------------------------------------------------

This mapper has been assigned the number 49. (that's 49 decimal)

Cart is marked "1993 SUPER HIK 4 in 1". The game lineup:

Master Fighter III (Dunno, not the "usual" SF/MK clone)
Bubbce Bobbce II (Bubble Bobble 2)
Gun-Nac
Zen Ninja (Zen: The Intergalactic Ninja)

---

This is very similar to the 7 in 1 I RE'd awhile back. It's made by the
same company, and the hardware is similar. The games don't appear to have
hacked out copyrights or anything. The menu code is at the end of the first
bank like usual.

Hardware consists of 2 TTL chips (74HC174 and 74HC157) and a pirate
MMC3 in a 40 pin DIP package.

---

There is 512K of PRG ROM, and 512K of CHR ROM

Standard MMC3 write addresses apply. This cart is somewhat interesting since
it is set up to play NROM titles as well. The menu shows 23 or so titles,
while only 4 appear when the game is run.

---

They used the WRAM output line to operate the 74174 on here which I thought
was somewhat clever. Since they did this, you must enable WRAM on the MMC3
before you can write to the register.

This register is accessed via writes to 06000h-07fffh.

7 bit 0
---------
BBPP xxxS

The B bits select which 128K page to work with for PRG AND CHR. The MMC3
can only "see" 128K of PRG and 128K of CHR at a time due to the way the
ROMs are wired. These B bits select the 128K page. bit 6 = LSB,
bit 7 = MSB.

The S bit controls the cart's mode. When set, the cart will be in MMC3
mode, and the MMC3 has full control of the 128K worth of PRG, and the
128K worth of CHR.

When the S bit is cleared, however, the cart reverts to "NROM compatibility
mode". The PRG ROM is "disconnected" from the MMC3 entirely, and the P bits
select which 32K PRG ROM bank will be used. CHR addressing is NOT affected
by this, presumably since you can select desired bank via the MMC3.

bit 5 is the MSB, and bit 4 is the LSB.

---

How to work it good:

When first powered up, the bank select register is cleared to 00h. This
selects the first 32K of PRG data, and the first 128K of CHR data.
There is a piece of bootstrap code which is loaded into 0400h and run.
It enables WRAM on the MMC3, and sets the bank select register to point
to the bank with the menu.

Link to source page

I get it this far :

Which pin of WRAM (MMC3) should I use for CLK :
WRAM /CE
WRAM CE
WRAM /WE

What are the other components and their specifications? And how can I use them? I guess I have to put them between WRAM line and CLK.
Resistor
Capacitor
Diode

Dump name is Super HIK 4-in-1 [p1][!].nes :
File: Super HIK 4-in-1 [p1][!].nes
Soft-patched: No
CRC: BD25BDC0
SHA-1: C33C72C0FFE6D1F00739009E460C500A50404567
System: Famicom
Board: BMC SUPERHIK 4-IN-1, Mapper 49
PRG-ROM: 512k
CHR-ROM: 512k
Battery: No
Dump: Unknown

Mapper 49 Info

Posted: **Thu Dec 22, 2011 5:27 pm**

To the best of my ability:
The resistor is 100 ohms (brown black brown gold)
The capacitor is probably more than 100pF and less than 10nF, but I can't see the numbers on it to tell you exactly what.
The diode is any standard small signal diode — 1n914, 1n4148, or similar.

Posted: **Thu Dec 22, 2011 5:46 pm**

The reset circuit resets the '174.

You probably use WRAM /CE for CLK since /WE shouldn't be decoded.

Posted: **Thu Dec 22, 2011 11:40 pm**

Oh reset circuit?! This is so much familiar :

I have this multicartridge also :

I think (and hope) it is the same reset circuit.

So here it is :

Is it necessary to set up P bits for NROM mode?! I feel that it is unnecessary.

Posted: **Fri Dec 23, 2011 2:24 am**

You don't have the '157 wired correctly. The most significant bit used from the MMC3 is A16 (so only 1M/1M games are supported).

BB bits go directly to A18:17 on PRG and CHR, not through the '157.

PP bits select PRG A16:15 in NROM mode. In MMC3 mode PRG A16:15 come from the MMC3.

The remaining two multiplexers are for PRG A14:13. In NROM mode they come from CPU A14:13, in MMC3 mode they come from the MMC3.

Posted: **Fri Dec 23, 2011 11:45 am**

Then why not just omit 157, I don't want to run any NROM game on this cartridge. So that it will be like this :

This is my conclusion :
CLK must be always low, by selecting a game on the menu it writes A register 81(10@BB) or 41(01@BB) or C1 (11@BB) to 6000h~7FFFh so that WRAM /CE(?) raise from LOW to HIGH and triggers CLK, at this moment BB bits strike D0 and D1 with 01 or 10 or 11 and then Q0 and Q1 latch those signal at 01 or 10 or 11 and supply it to A18 and A17 of PRG and CHR so that MMC3 just see the 128KB + 128KB of PRG and CHR and then the selected game runs!

By pushing the rest button the reset circuit sends a LOW signal to MR and causes Q0 and Q1 to be 00 so that first 128KB + 128KB of PRG and CHR can be seen by MMC3 and it returns to the menu selection screen.

Is my conclusion right?

Can someone explain what happens when the first power up and how the selection screen comes up?

Are you sure about WRAM /CE? It must be always low for CLK.

Posted: **Fri Dec 23, 2011 4:09 pm**

Yes you can omit the '157 assuming the menu does not test its functionality. You should also probably use a '74 instead of '174 since it's a more common part.

WRAM /CE is used because the register is triggered on the rising edge, which corresponds to the end of the Phi2 memory-access cycle where data is driven on the bus. Basically the CLK signal stays in the high state, then on access is strobed low briefly while WRAM is being accessed. If you were to use positive CE you would clock the register immediately through the asynchronous address decoding during Phi1 and the data will not be valid.

Pushing reset doesn't drive the line low, pushing reset causes Phi2 to go into high impedance so the capacitor doesn't receive any current and discharges through the resistor. Once the system starts again Phi2 sources current but since the capacitor is drained it must charge again. The time constant is selected so that after power is applied there is large enough delay before /RESET is brought high by the capacitor so that the registers are guaranteed to be reset (00). You could easily make a multicart for any mapper solely using a counter and reset circuit.

Posted: **Sat Dec 24, 2011 1:37 pm**

Any other mistake on this :

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1993 Super HiK 4 in 1 Hardware Remake

1993 Super HiK 4 in 1 Hardware Remake